| Jit Loon Lim | 4c249f1 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. |
| 3 | * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. |
| 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #ifndef PLAT_SOCFPGA_DEF_H |
| 9 | #define PLAT_SOCFPGA_DEF_H |
| 10 | |
| 11 | #include "agilex5_memory_controller.h" |
| 12 | #include "agilex5_system_manager.h" |
| 13 | #include <platform_def.h> |
| 14 | |
| 15 | /* Platform Setting */ |
| 16 | #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX5 |
| 17 | #define BOOT_SOURCE BOOT_SOURCE_SDMMC |
| 18 | #define MMC_DEVICE_TYPE 1 /* MMC = 0, SD = 1 */ |
| 19 | #define XLAT_TABLES_V2 U(1) |
| 20 | #define PLAT_PRIMARY_CPU_A55 0x000 |
| 21 | #define PLAT_PRIMARY_CPU_A76 0x200 |
| 22 | #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF2_SHIFT |
| 23 | #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT |
| 24 | #define PLAT_L2_RESET_REQ 0xB007C0DE |
| 25 | |
| 26 | /* System Counter */ /* TODO: Update back to 400MHz */ |
| 27 | #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (80000000) |
| 28 | #define PLAT_SYS_COUNTER_FREQ_IN_MHZ (80) |
| 29 | |
| 30 | /* FPGA config helpers */ |
| 31 | #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 |
| 32 | #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000 |
| 33 | |
| 34 | /* QSPI Setting */ |
| 35 | #define CAD_QSPIDATA_OFST 0x10900000 |
| 36 | #define CAD_QSPI_OFFSET 0x108d2000 |
| 37 | |
| 38 | /* Register Mapping */ |
| 39 | #define SOCFPGA_CCU_NOC_REG_BASE 0x1c000000 |
| 40 | #define SOCFPGA_F2SDRAMMGR_REG_BASE 0x18001000 |
| 41 | |
| 42 | #define SOCFPGA_MMC_REG_BASE 0x10808000 |
| 43 | #define SOCFPGA_MEMCTRL_REG_BASE 0x108CC000 |
| 44 | #define SOCFPGA_RSTMGR_REG_BASE 0x10d11000 |
| 45 | #define SOCFPGA_SYSMGR_REG_BASE 0x10d12000 |
| 46 | #define SOCFPGA_PINMUX_REG_BASE 0x10d13000 |
| 47 | #define SOCFPGA_NAND_REG_BASE 0x10B80000 |
| 48 | |
| 49 | #define SOCFPGA_L4_PER_SCR_REG_BASE 0x10d21000 |
| 50 | #define SOCFPGA_L4_SYS_SCR_REG_BASE 0x10d21100 |
| 51 | #define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0x10d21200 |
| 52 | #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0x10d21300 |
| 53 | |
| 54 | /* Define maximum page size for NAND flash devices */ |
| 55 | #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) |
| 56 | |
| 57 | /******************************************************************************* |
| 58 | * Platform memory map related constants |
| 59 | ******************************************************************************/ |
| 60 | #define DRAM_BASE (0x80000000) |
| 61 | #define DRAM_SIZE (0x80000000) |
| 62 | |
| 63 | #define OCRAM_BASE (0x00000000) |
| 64 | #define OCRAM_SIZE (0x00080000) |
| 65 | |
| 66 | #define MEM64_BASE (0x0080000000) |
| 67 | #define MEM64_SIZE (0x0080000000) |
| 68 | |
| 69 | //128MB PSS |
| 70 | #define PSS_BASE (0x10000000) |
| 71 | #define PSS_SIZE (0x08000000) |
| 72 | |
| 73 | //64MB MPFE |
| 74 | #define MPFE_BASE (0x18000000) |
| 75 | #define MPFE_SIZE (0x04000000) |
| 76 | |
| 77 | //16MB CCU |
| 78 | #define CCU_BASE (0x1C000000) |
| 79 | #define CCU_SIZE (0x01000000) |
| 80 | |
| 81 | //1MB GIC |
| 82 | #define GIC_BASE (0x1D000000) |
| 83 | #define GIC_SIZE (0x00100000) |
| 84 | |
| 85 | #define BL2_BASE (0x00000000) |
| 86 | #define BL2_LIMIT (0x0001b000) |
| 87 | |
| 88 | #define BL31_BASE (0x80000000) |
| 89 | #define BL31_LIMIT (0x82000000) |
| 90 | |
| 91 | /******************************************************************************* |
| 92 | * UART related constants |
| 93 | ******************************************************************************/ |
| 94 | #define PLAT_UART0_BASE (0x10C02000) |
| 95 | #define PLAT_UART1_BASE (0x10C02100) |
| 96 | |
| 97 | /******************************************************************************* |
| 98 | * GIC related constants |
| 99 | ******************************************************************************/ |
| 100 | #define PLAT_GIC_BASE (0x1D000000) |
| 101 | #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x20000) |
| 102 | #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x00000) |
| 103 | #define PLAT_GICR_BASE (PLAT_GIC_BASE + 0x60000) |
| 104 | |
| 105 | #define PLAT_INTEL_SOCFPGA_GICR_BASE PLAT_GICR_BASE |
| 106 | |
| 107 | /******************************************************************************* |
| 108 | * SDMMC related pointer function |
| 109 | ******************************************************************************/ |
| 110 | #define SDMMC_READ_BLOCKS sdmmc_read_blocks |
| 111 | #define SDMMC_WRITE_BLOCKS sdmmc_write_blocks |
| 112 | |
| 113 | /******************************************************************************* |
| 114 | * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset |
| 115 | * is done and HPS should trigger warm reset via RMR_EL3. |
| 116 | ******************************************************************************/ |
| 117 | #define L2_RESET_DONE_REG 0x10D12218 |
| 118 | |
| 119 | #endif /* PLAT_SOCFPGA_DEF_H */ |