| Juan Pablo Conde | c9fe7ce | 2023-07-05 11:57:50 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2023, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef CORTEX_GELAS_H |
| 8 | #define CORTEX_GELAS_H |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
| 12 | #define CORTEX_GELAS_MIDR U(0x410FD8B0) |
| 13 | |
| 14 | /******************************************************************************* |
| 15 | * CPU Extended Control register specific definitions |
| 16 | ******************************************************************************/ |
| 17 | #define CORTEX_GELAS_IMP_CPUECTLR_EL1 S3_0_C15_C1_5 |
| 18 | |
| 19 | /******************************************************************************* |
| 20 | * CPU Power Control register specific definitions |
| 21 | ******************************************************************************/ |
| 22 | #define CORTEX_GELAS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 23 | #define CORTEX_GELAS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) |
| 24 | |
| 25 | /******************************************************************************* |
| 26 | * SME Control registers |
| 27 | ******************************************************************************/ |
| 28 | #define CORTEX_GELAS_SVCRSM S0_3_C4_C2_3 |
| 29 | #define CORTEX_GELAS_SVCRZA S0_3_C4_C4_3 |
| 30 | |
| 31 | #endif /* CORTEX_GELAS_H */ |