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Harrison Mutaie5004c12023-05-23 17:28:03 +01001/*
2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef CORTEX_A715_H
8#define CORTEX_A715_H
9
10#define CORTEX_A715_MIDR U(0x410FD4D0)
11
12/* Cortex-A715 loop count for CVE-2022-23960 mitigation */
13#define CORTEX_A715_BHB_LOOP_COUNT U(38)
14
15/*******************************************************************************
16 * CPU Extended Control register specific definitions
17 ******************************************************************************/
18#define CORTEX_A715_CPUECTLR_EL1 S3_0_C15_C1_4
19
20/*******************************************************************************
21 * CPU Power Control register specific definitions
22 ******************************************************************************/
23#define CORTEX_A715_CPUPWRCTLR_EL1 S3_0_C15_C2_7
24#define CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
25
26#endif /* CORTEX_A715_H */