Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / 4b32e6214d67f6e10c8899ca94e631e3a7fca841 / . / plat / nvidia / tegra / soc / t186 / platform_t186.mk
blob: c9053238bc5edfacfd58a34cbbb20886fabce1f2 [file] [log] [blame]
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]1#
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530[diff] [blame]2# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]3#
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4# SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]5#
6
7# platform configs
Varun Wadekar4c7fa502016-12-13 13:13:42 -0800[diff] [blame]8ENABLE_AFI_DEVICE := 1
9$(eval $(call add_define,ENABLE_AFI_DEVICE))
10
Varun Wadekara0f26972016-03-11 17:18:51 -0800[diff] [blame]11ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 1
12$(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS))
13
Varun Wadekar94701ff2016-05-23 11:47:34 -0700[diff] [blame]14RELOCATE_TO_BL31_BASE := 1
15$(eval $(call add_define,RELOCATE_TO_BL31_BASE))
16
Varun Wadekarad2824f2016-03-28 13:44:35 -0700[diff] [blame]17ENABLE_CHIP_VERIFICATION_HARNESS := 0
18$(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS))
19
Varun Wadekar6cb25f92016-12-19 11:17:54 -0800[diff] [blame]20ENABLE_SMMU_DEVICE := 1
21$(eval $(call add_define,ENABLE_SMMU_DEVICE))
22
Pritesh Raithatha0de6e532017-01-24 13:49:46 +0530[diff] [blame]23NUM_SMMU_DEVICES := 1
24$(eval $(call add_define,NUM_SMMU_DEVICES))
25
Varun Wadekar94701ff2016-05-23 11:47:34 -0700[diff] [blame]26RESET_TO_BL31 := 1
27
28PROGRAMMABLE_RESET_ADDRESS := 1
29
30COLD_BOOT_SINGLE_CPU := 1
31
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]32# platform settings
Varun Wadekar94d85322015-11-30 12:05:04 -0800[diff] [blame]33TZDRAM_BASE := 0x30000000
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]34$(eval $(call add_define,TZDRAM_BASE))
35
36PLATFORM_CLUSTER_COUNT := 2
37$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
38
39PLATFORM_MAX_CPUS_PER_CLUSTER := 4
40$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
41
Varun Wadekard64db962016-09-23 14:28:16 -0700[diff] [blame]42MAX_XLAT_TABLES := 24
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]43$(eval $(call add_define,MAX_XLAT_TABLES))
44
Varun Wadekard64db962016-09-23 14:28:16 -0700[diff] [blame]45MAX_MMAP_REGIONS := 24
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]46$(eval $(call add_define,MAX_MMAP_REGIONS))
47
48# platform files
49PLAT_INCLUDES += -I${SOC_DIR}/drivers/include
50
51BL31_SOURCES += lib/cpus/aarch64/denver.S \
52 lib/cpus/aarch64/cortex_a57.S \
Pritesh Raithathac88654f2017-01-02 20:11:32 +0530[diff] [blame]53 ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \
Varun Wadekarbd2b4142016-12-12 16:46:44 -0800[diff] [blame]54 ${COMMON_DIR}/drivers/smmu/smmu.c \
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]55 ${SOC_DIR}/drivers/mce/mce.c \
56 ${SOC_DIR}/drivers/mce/ari.c \
57 ${SOC_DIR}/drivers/mce/nvg.c \
58 ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530[diff] [blame]59 ${SOC_DIR}/plat_memctrl.c \
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]60 ${SOC_DIR}/plat_psci_handlers.c \
61 ${SOC_DIR}/plat_setup.c \
62 ${SOC_DIR}/plat_secondary.c \
Varun Wadekar93bed2a2016-03-18 13:07:33 -0700[diff] [blame]63 ${SOC_DIR}/plat_sip_calls.c \
Pritesh Raithathac88654f2017-01-02 20:11:32 +0530[diff] [blame]64 ${SOC_DIR}/plat_smmu.c \
Varun Wadekar93bed2a2016-03-18 13:07:33 -0700[diff] [blame]65 ${SOC_DIR}/plat_trampoline.S
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530[diff] [blame]66