Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / 4a826ddad8ea0fc5ce09709f534efb72cc33611c / . / arch / system / gic / gic.h
blob: e4beb56a8779d66a9d38fb43f59bca61672afe1d [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]1/*
Dan Handleyab2d31e2013-12-02 19:25:12 +0000[diff] [blame]2 * Copyright (c) 2013, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __GIC_H__
32#define __GIC_H__
33
34#define MAX_SPIS 480
35#define MAX_PPIS 14
36#define MAX_SGIS 16
37
38#define GRP0 0
39#define GRP1 1
40#define MAX_PRI_VAL 0xff
41
42#define ENABLE_GRP0 (1 << 0)
43#define ENABLE_GRP1 (1 << 1)
44
45/* Distributor interface definitions */
46#define GICD_CTLR 0x0
47#define GICD_TYPER 0x4
48#define GICD_IGROUPR 0x80
49#define GICD_ISENABLER 0x100
50#define GICD_ICENABLER 0x180
51#define GICD_ISPENDR 0x200
52#define GICD_ICPENDR 0x280
53#define GICD_ISACTIVER 0x300
54#define GICD_ICACTIVER 0x380
55#define GICD_IPRIORITYR 0x400
56#define GICD_ITARGETSR 0x800
57#define GICD_ICFGR 0xC00
58#define GICD_SGIR 0xF00
59#define GICD_CPENDSGIR 0xF10
60#define GICD_SPENDSGIR 0xF20
61
62#define IGROUPR_SHIFT 5
63#define ISENABLER_SHIFT 5
64#define ICENABLER_SHIFT ISENABLER_SHIFT
65#define ISPENDR_SHIFT 5
66#define ICPENDR_SHIFT ISPENDR_SHIFT
67#define ISACTIVER_SHIFT 5
68#define ICACTIVER_SHIFT ISACTIVER_SHIFT
69#define IPRIORITYR_SHIFT 2
70#define ITARGETSR_SHIFT 2
71#define ICFGR_SHIFT 4
72#define CPENDSGIR_SHIFT 2
73#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT
74
75/* GICD_TYPER bit definitions */
76#define IT_LINES_NO_MASK 0x1f
77
78/* Physical CPU Interface registers */
79#define GICC_CTLR 0x0
80#define GICC_PMR 0x4
81#define GICC_BPR 0x8
82#define GICC_IAR 0xC
83#define GICC_EOIR 0x10
84#define GICC_RPR 0x14
85#define GICC_HPPIR 0x18
86#define GICC_IIDR 0xFC
87#define GICC_DIR 0x1000
88#define GICC_PRIODROP GICC_EOIR
89
90/* GICC_CTLR bit definitions */
91#define EOI_MODE_NS (1 << 10)
92#define EOI_MODE_S (1 << 9)
93#define IRQ_BYP_DIS_GRP1 (1 << 8)
94#define FIQ_BYP_DIS_GRP1 (1 << 7)
95#define IRQ_BYP_DIS_GRP0 (1 << 6)
96#define FIQ_BYP_DIS_GRP0 (1 << 5)
97#define CBPR (1 << 4)
98#define FIQ_EN (1 << 3)
99#define ACK_CTL (1 << 2)
100
101/* GICC_IIDR bit masks and shifts */
102#define GICC_IIDR_PID_SHIFT 20
103#define GICC_IIDR_ARCH_SHIFT 16
104#define GICC_IIDR_REV_SHIFT 12
105#define GICC_IIDR_IMP_SHIFT 0
106
107#define GICC_IIDR_PID_MASK 0xfff
108#define GICC_IIDR_ARCH_MASK 0xf
109#define GICC_IIDR_REV_MASK 0xf
110#define GICC_IIDR_IMP_MASK 0xfff
111
112/* HYP view virtual CPU Interface registers */
113#define GICH_CTL 0x0
114#define GICH_VTR 0x4
115#define GICH_ELRSR0 0x30
116#define GICH_ELRSR1 0x34
117#define GICH_APR0 0xF0
118#define GICH_LR_BASE 0x100
119
120/* Virtual CPU Interface registers */
121#define GICV_CTL 0x0
122#define GICV_PRIMASK 0x4
123#define GICV_BP 0x8
124#define GICV_INTACK 0xC
125#define GICV_EOI 0x10
126#define GICV_RUNNINGPRI 0x14
127#define GICV_HIGHESTPEND 0x18
128#define GICV_DEACTIVATE 0x1000
129
130/* GICv3 Re-distributor interface registers & shifts */
131#define GICR_PCPUBASE_SHIFT 0x11
132#define GICR_WAKER 0x14
133
134/* GICR_WAKER bit definitions */
135#define WAKER_CA (1UL << 2)
136#define WAKER_PS (1UL << 1)
137
138/* GICv3 ICC_SRE register bit definitions*/
139#define ICC_SRE_EN (1UL << 3)
140#define ICC_SRE_SRE (1UL << 0)
141
142#ifndef __ASSEMBLY__
143
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100[diff] [blame]144#include <gic_v2.h>
145#include <gic_v3.h>
146
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]147/*******************************************************************************
148 * Function prototypes
149 ******************************************************************************/
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100[diff] [blame]150
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]151extern unsigned int gicd_read_igroupr(unsigned int, unsigned int);
152extern unsigned int gicd_read_isenabler(unsigned int, unsigned int);
153extern unsigned int gicd_read_icenabler(unsigned int, unsigned int);
154extern unsigned int gicd_read_ispendr(unsigned int, unsigned int);
155extern unsigned int gicd_read_icpendr(unsigned int, unsigned int);
156extern unsigned int gicd_read_isactiver(unsigned int, unsigned int);
157extern unsigned int gicd_read_icactiver(unsigned int, unsigned int);
158extern unsigned int gicd_read_ipriorityr(unsigned int, unsigned int);
159extern unsigned int gicd_read_itargetsr(unsigned int, unsigned int);
160extern unsigned int gicd_read_icfgr(unsigned int, unsigned int);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]161extern unsigned int gicd_read_cpendsgir(unsigned int, unsigned int);
162extern unsigned int gicd_read_spendsgir(unsigned int, unsigned int);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]163extern void gicd_write_igroupr(unsigned int, unsigned int, unsigned int);
164extern void gicd_write_isenabler(unsigned int, unsigned int, unsigned int);
165extern void gicd_write_icenabler(unsigned int, unsigned int, unsigned int);
166extern void gicd_write_ispendr(unsigned int, unsigned int, unsigned int);
167extern void gicd_write_icpendr(unsigned int, unsigned int, unsigned int);
168extern void gicd_write_isactiver(unsigned int, unsigned int, unsigned int);
169extern void gicd_write_icactiver(unsigned int, unsigned int, unsigned int);
170extern void gicd_write_ipriorityr(unsigned int, unsigned int, unsigned int);
171extern void gicd_write_itargetsr(unsigned int, unsigned int, unsigned int);
172extern void gicd_write_icfgr(unsigned int, unsigned int, unsigned int);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]173extern void gicd_write_cpendsgir(unsigned int, unsigned int, unsigned int);
174extern void gicd_write_spendsgir(unsigned int, unsigned int, unsigned int);
175extern unsigned int gicd_get_igroupr(unsigned int, unsigned int);
176extern void gicd_set_igroupr(unsigned int, unsigned int);
177extern void gicd_clr_igroupr(unsigned int, unsigned int);
178extern void gicd_set_isenabler(unsigned int, unsigned int);
179extern void gicd_set_icenabler(unsigned int, unsigned int);
180extern void gicd_set_ispendr(unsigned int, unsigned int);
181extern void gicd_set_icpendr(unsigned int, unsigned int);
182extern void gicd_set_isactiver(unsigned int, unsigned int);
183extern void gicd_set_icactiver(unsigned int, unsigned int);
184extern void gicd_set_ipriorityr(unsigned int, unsigned int, unsigned int);
185extern void gicd_set_itargetsr(unsigned int, unsigned int, unsigned int);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]186
187/* GICv3 functions */
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100[diff] [blame]188
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]189extern unsigned int read_icc_sre_el1(void);
190extern unsigned int read_icc_sre_el2(void);
191extern unsigned int read_icc_sre_el3(void);
192extern void write_icc_sre_el1(unsigned int);
193extern void write_icc_sre_el2(unsigned int);
194extern void write_icc_sre_el3(unsigned int);
195extern void write_icc_pmr_el1(unsigned int);
196
197#endif /*__ASSEMBLY__*/
198
199#endif /* __GIC_H__ */
200