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git01.mediatek.com / filogic / atf / 4a3811fa0665542f41ce1f2ac1b066487610fe4c / . / drivers / arm / css / mhu / css_mhu_doorbell.c
blob: 479bb21b3c8579c3e6f669843455477532585e12 [file] [log] [blame]
Samarth Parikh59cfa132017-11-23 14:23:21 +0530[diff] [blame]1/*
Aditya Angadi7b424ba2019-12-31 10:14:32 +0530[diff] [blame]2 * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
Samarth Parikh59cfa132017-11-23 14:23:21 +0530[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Samarth Parikh59cfa132017-11-23 14:23:21 +0530[diff] [blame]7#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]8
9#include <arch_helpers.h>
Antonio Nino Diaz1b0c6f12019-01-23 21:08:43 +0000[diff] [blame]10#include <drivers/arm/css/css_mhu_doorbell.h>
Antonio Nino Diazc30db5b2019-01-23 20:37:32 +0000[diff] [blame]11#include <drivers/arm/css/scmi.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]12
Roberto Vargas85664f52018-02-12 12:36:17 +0000[diff] [blame]13void mhu_ring_doorbell(struct scmi_channel_plat_info *plat_info)
Samarth Parikh59cfa132017-11-23 14:23:21 +0530[diff] [blame]14{
15 MHU_RING_DOORBELL(plat_info->db_reg_addr,
16 plat_info->db_modify_mask,
17 plat_info->db_preserve_mask);
Samarth Parikh59cfa132017-11-23 14:23:21 +0530[diff] [blame]18}
19
Roberto Vargas85664f52018-02-12 12:36:17 +0000[diff] [blame]20void mhuv2_ring_doorbell(struct scmi_channel_plat_info *plat_info)
Samarth Parikh59cfa132017-11-23 14:23:21 +0530[diff] [blame]21{
Aditya Angadi7b424ba2019-12-31 10:14:32 +0530[diff] [blame]22 uintptr_t mhuv2_base = plat_info->db_reg_addr & MHU_V2_FRAME_BASE_MASK;
23
Samarth Parikh59cfa132017-11-23 14:23:21 +0530[diff] [blame]24 /* wake receiver */
Aditya Angadi7b424ba2019-12-31 10:14:32 +0530[diff] [blame]25 MHU_V2_ACCESS_REQUEST(mhuv2_base);
Samarth Parikh59cfa132017-11-23 14:23:21 +0530[diff] [blame]26
27 /* wait for receiver to acknowledge its ready */
Aditya Angadi7b424ba2019-12-31 10:14:32 +0530[diff] [blame]28 while (MHU_V2_IS_ACCESS_READY(mhuv2_base) == 0)
Samarth Parikh59cfa132017-11-23 14:23:21 +0530[diff] [blame]29 ;
30
31 MHU_RING_DOORBELL(plat_info->db_reg_addr,
32 plat_info->db_modify_mask,
33 plat_info->db_preserve_mask);
34
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000[diff] [blame]35 /* clear the access request for the receiver */
Aditya Angadi7b424ba2019-12-31 10:14:32 +0530[diff] [blame]36 MHU_V2_CLEAR_REQUEST(mhuv2_base);
Samarth Parikh59cfa132017-11-23 14:23:21 +0530[diff] [blame]37}