Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 1 | /* |
Boyan Karatotev | 496ae96 | 2023-04-05 11:02:22 +0100 | [diff] [blame^] | 2 | * Copyright (c) 2019-2023, Arm Limited. All rights reserved. |
Varun Wadekar | 9030a6c | 2022-03-09 22:04:00 +0000 | [diff] [blame] | 3 | * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved. |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #include <arch.h> |
| 9 | #include <asm_macros.S> |
| 10 | #include <common/bl_common.h> |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 11 | #include <cortex_a78_ae.h> |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 12 | #include <cpu_macros.S> |
| 13 | #include <plat_macros.S> |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 14 | #include "wa_cve_2022_23960_bhb_vector.S" |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 15 | |
| 16 | /* Hardware handled coherency */ |
| 17 | #if HW_ASSISTED_COHERENCY == 0 |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 18 | #error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled" |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 19 | #endif |
| 20 | |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 21 | #if WORKAROUND_CVE_2022_23960 |
| 22 | wa_cve_2022_23960_bhb_vector_table CORTEX_A78_AE_BHB_LOOP_COUNT, cortex_a78_ae |
| 23 | #endif /* WORKAROUND_CVE_2022_23960 */ |
| 24 | |
Boyan Karatotev | 496ae96 | 2023-04-05 11:02:22 +0100 | [diff] [blame^] | 25 | workaround_reset_start cortex_a78_ae, ERRATUM(1941500), ERRATA_A78_AE_1941500 |
Varun Wadekar | 0914fc4 | 2021-07-27 02:32:29 -0700 | [diff] [blame] | 26 | /* Set bit 8 in ECTLR_EL1 */ |
| 27 | mrs x0, CORTEX_A78_AE_CPUECTLR_EL1 |
| 28 | bic x0, x0, #CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 |
| 29 | msr CORTEX_A78_AE_CPUECTLR_EL1, x0 |
Boyan Karatotev | 496ae96 | 2023-04-05 11:02:22 +0100 | [diff] [blame^] | 30 | workaround_reset_end cortex_a78_ae, ERRATUM(1941500) |
Varun Wadekar | 0914fc4 | 2021-07-27 02:32:29 -0700 | [diff] [blame] | 31 | |
Boyan Karatotev | 496ae96 | 2023-04-05 11:02:22 +0100 | [diff] [blame^] | 32 | check_erratum_range cortex_a78_ae, ERRATUM(1941500), CPU_REV(0, 0), CPU_REV(0, 1) |
Varun Wadekar | 0914fc4 | 2021-07-27 02:32:29 -0700 | [diff] [blame] | 33 | |
Boyan Karatotev | 496ae96 | 2023-04-05 11:02:22 +0100 | [diff] [blame^] | 34 | workaround_reset_start cortex_a78_ae, ERRATUM(1951502), ERRATA_A78_AE_1951502 |
Varun Wadekar | a3110ad | 2021-07-27 00:39:40 -0700 | [diff] [blame] | 35 | msr S3_6_c15_c8_0, xzr |
| 36 | ldr x0, =0x10E3900002 |
| 37 | msr S3_6_c15_c8_2, x0 |
| 38 | ldr x0, =0x10FFF00083 |
| 39 | msr S3_6_c15_c8_3, x0 |
| 40 | ldr x0, =0x2001003FF |
| 41 | msr S3_6_c15_c8_1, x0 |
| 42 | |
| 43 | mov x0, #1 |
| 44 | msr S3_6_c15_c8_0, x0 |
| 45 | ldr x0, =0x10E3800082 |
| 46 | msr S3_6_c15_c8_2, x0 |
| 47 | ldr x0, =0x10FFF00083 |
| 48 | msr S3_6_c15_c8_3, x0 |
| 49 | ldr x0, =0x2001003FF |
| 50 | msr S3_6_c15_c8_1, x0 |
| 51 | |
| 52 | mov x0, #2 |
| 53 | msr S3_6_c15_c8_0, x0 |
| 54 | ldr x0, =0x10E3800200 |
| 55 | msr S3_6_c15_c8_2, x0 |
| 56 | ldr x0, =0x10FFF003E0 |
| 57 | msr S3_6_c15_c8_3, x0 |
| 58 | ldr x0, =0x2001003FF |
| 59 | msr S3_6_c15_c8_1, x0 |
Boyan Karatotev | 496ae96 | 2023-04-05 11:02:22 +0100 | [diff] [blame^] | 60 | workaround_reset_end cortex_a78_ae, ERRATUM(1951502) |
Varun Wadekar | a3110ad | 2021-07-27 00:39:40 -0700 | [diff] [blame] | 61 | |
Boyan Karatotev | 496ae96 | 2023-04-05 11:02:22 +0100 | [diff] [blame^] | 62 | check_erratum_range cortex_a78_ae, ERRATUM(1951502), CPU_REV(0, 0), CPU_REV(0, 1) |
Varun Wadekar | a3110ad | 2021-07-27 00:39:40 -0700 | [diff] [blame] | 63 | |
Boyan Karatotev | 496ae96 | 2023-04-05 11:02:22 +0100 | [diff] [blame^] | 64 | workaround_reset_start cortex_a78_ae, ERRATUM(2376748), ERRATA_A78_AE_2376748 |
Varun Wadekar | 9030a6c | 2022-03-09 22:04:00 +0000 | [diff] [blame] | 65 | /* ------------------------------------------------------- |
| 66 | * Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to |
| 67 | * behave like PLD/PRFM LD and not cause invalidations to |
| 68 | * other PE caches. There might be a small performance |
| 69 | * degradation to this workaround for certain workloads |
| 70 | * that share data. |
| 71 | * ------------------------------------------------------- |
| 72 | */ |
| 73 | mrs x0, CORTEX_A78_AE_ACTLR2_EL1 |
| 74 | orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_0 |
| 75 | msr CORTEX_A78_AE_ACTLR2_EL1, x0 |
Boyan Karatotev | 496ae96 | 2023-04-05 11:02:22 +0100 | [diff] [blame^] | 76 | workaround_reset_end cortex_a78_ae, ERRATUM(2376748) |
Varun Wadekar | 9030a6c | 2022-03-09 22:04:00 +0000 | [diff] [blame] | 77 | |
Boyan Karatotev | 496ae96 | 2023-04-05 11:02:22 +0100 | [diff] [blame^] | 78 | check_erratum_range cortex_a78_ae, ERRATUM(2376748), CPU_REV(0, 0), CPU_REV(0, 1) |
Varun Wadekar | ac6bf2e | 2022-03-09 22:20:32 +0000 | [diff] [blame] | 79 | |
Boyan Karatotev | 496ae96 | 2023-04-05 11:02:22 +0100 | [diff] [blame^] | 80 | workaround_reset_start cortex_a78_ae, ERRATUM(2395408), ERRATA_A78_AE_2395408 |
Varun Wadekar | ac6bf2e | 2022-03-09 22:20:32 +0000 | [diff] [blame] | 81 | /* -------------------------------------------------------- |
| 82 | * Disable folding of demand requests into older prefetches |
| 83 | * with L2 miss requests outstanding by setting the |
| 84 | * CPUACTLR2_EL1[40] to 1. |
| 85 | * -------------------------------------------------------- |
| 86 | */ |
| 87 | mrs x0, CORTEX_A78_AE_ACTLR2_EL1 |
| 88 | orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_40 |
| 89 | msr CORTEX_A78_AE_ACTLR2_EL1, x0 |
Boyan Karatotev | 496ae96 | 2023-04-05 11:02:22 +0100 | [diff] [blame^] | 90 | workaround_reset_end cortex_a78_ae, ERRATUM(2395408) |
Varun Wadekar | ac6bf2e | 2022-03-09 22:20:32 +0000 | [diff] [blame] | 91 | |
Boyan Karatotev | 496ae96 | 2023-04-05 11:02:22 +0100 | [diff] [blame^] | 92 | check_erratum_range cortex_a78_ae, ERRATUM(2395408), CPU_REV(0, 0), CPU_REV(0, 1) |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 93 | |
Boyan Karatotev | 496ae96 | 2023-04-05 11:02:22 +0100 | [diff] [blame^] | 94 | workaround_reset_start cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 95 | #if IMAGE_BL31 |
| 96 | /* |
| 97 | * The Cortex-A78AE generic vectors are overridden to apply errata |
| 98 | * mitigation on exception entry from lower ELs. |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 99 | */ |
Boyan Karatotev | 496ae96 | 2023-04-05 11:02:22 +0100 | [diff] [blame^] | 100 | override_vector_table wa_cve_vbar_cortex_a78_ae |
| 101 | #endif /* IMAGE_BL31 */ |
| 102 | workaround_reset_end cortex_a78_ae, CVE(2022, 23960) |
Varun Wadekar | a3110ad | 2021-07-27 00:39:40 -0700 | [diff] [blame] | 103 | |
Boyan Karatotev | 496ae96 | 2023-04-05 11:02:22 +0100 | [diff] [blame^] | 104 | check_erratum_chosen cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
Varun Wadekar | 0914fc4 | 2021-07-27 02:32:29 -0700 | [diff] [blame] | 105 | |
Boyan Karatotev | 496ae96 | 2023-04-05 11:02:22 +0100 | [diff] [blame^] | 106 | cpu_reset_func_start cortex_a78_ae |
Andre Przywara | 0b7f1b0 | 2023-03-21 13:53:19 +0000 | [diff] [blame] | 107 | #if ENABLE_FEAT_AMU |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 108 | /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ |
| 109 | mrs x0, actlr_el3 |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 110 | bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 111 | msr actlr_el3, x0 |
| 112 | |
| 113 | /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ |
| 114 | mrs x0, actlr_el2 |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 115 | bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 116 | msr actlr_el2, x0 |
| 117 | |
| 118 | /* Enable group0 counters */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 119 | mov x0, #CORTEX_A78_AMU_GROUP0_MASK |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 120 | msr CPUAMCNTENSET0_EL0, x0 |
| 121 | |
| 122 | /* Enable group1 counters */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 123 | mov x0, #CORTEX_A78_AMU_GROUP1_MASK |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 124 | msr CPUAMCNTENSET1_EL0, x0 |
Varun Wadekar | a3110ad | 2021-07-27 00:39:40 -0700 | [diff] [blame] | 125 | #endif |
Boyan Karatotev | 496ae96 | 2023-04-05 11:02:22 +0100 | [diff] [blame^] | 126 | cpu_reset_func_end cortex_a78_ae |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 127 | |
| 128 | /* ------------------------------------------------------- |
| 129 | * HW will do the cache maintenance while powering down |
| 130 | * ------------------------------------------------------- |
| 131 | */ |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 132 | func cortex_a78_ae_core_pwr_dwn |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 133 | /* ------------------------------------------------------- |
| 134 | * Enable CPU power down bit in power control register |
| 135 | * ------------------------------------------------------- |
| 136 | */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 137 | mrs x0, CORTEX_A78_CPUPWRCTLR_EL1 |
| 138 | orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT |
| 139 | msr CORTEX_A78_CPUPWRCTLR_EL1, x0 |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 140 | isb |
| 141 | ret |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 142 | endfunc cortex_a78_ae_core_pwr_dwn |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 143 | |
Boyan Karatotev | 496ae96 | 2023-04-05 11:02:22 +0100 | [diff] [blame^] | 144 | errata_report_shim cortex_a78_ae |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 145 | |
| 146 | /* ------------------------------------------------------- |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 147 | * This function provides cortex_a78_ae specific |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 148 | * register information for crash reporting. |
| 149 | * It needs to return with x6 pointing to |
| 150 | * a list of register names in ascii and |
| 151 | * x8 - x15 having values of registers to be |
| 152 | * reported. |
| 153 | * ------------------------------------------------------- |
| 154 | */ |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 155 | .section .rodata.cortex_a78_ae_regs, "aS" |
| 156 | cortex_a78_ae_regs: /* The ascii list of register names to be reported */ |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 157 | .asciz "cpuectlr_el1", "" |
| 158 | |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 159 | func cortex_a78_ae_cpu_reg_dump |
| 160 | adr x6, cortex_a78_ae_regs |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 161 | mrs x8, CORTEX_A78_CPUECTLR_EL1 |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 162 | ret |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 163 | endfunc cortex_a78_ae_cpu_reg_dump |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 164 | |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 165 | declare_cpu_ops cortex_a78_ae, CORTEX_A78_AE_MIDR, \ |
Varun Wadekar | a3110ad | 2021-07-27 00:39:40 -0700 | [diff] [blame] | 166 | cortex_a78_ae_reset_func, \ |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 167 | cortex_a78_ae_core_pwr_dwn |