Paul Beesley | fc9ee36 | 2019-03-07 15:47:15 +0000 | [diff] [blame] | 1 | CPU Reset |
| 2 | ========= |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 4 | This document describes the high-level design of the framework to handle CPU |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 5 | resets in Trusted Firmware-A (TF-A). It also describes how the platform |
| 6 | integrator can tailor this code to the system configuration to some extent, |
| 7 | resulting in a simplified and more optimised boot flow. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 8 | |
| 9 | This document should be used in conjunction with the `Firmware Design`_, which |
| 10 | provides greater implementation details around the reset code, specifically |
| 11 | for the cold boot path. |
| 12 | |
| 13 | General reset code flow |
| 14 | ----------------------- |
| 15 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 16 | The TF-A reset code is implemented in BL1 by default. The following high-level |
| 17 | diagram illustrates this: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 18 | |
| 19 | |Default reset code flow| |
| 20 | |
| 21 | This diagram shows the default, unoptimised reset flow. Depending on the system |
| 22 | configuration, some of these steps might be unnecessary. The following sections |
| 23 | guide the platform integrator by indicating which build options exclude which |
| 24 | steps, depending on the capability of the platform. |
| 25 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 26 | Note: If BL31 is used as the TF-A entry point instead of BL1, the diagram |
| 27 | above is still relevant, as all these operations will occur in BL31 in |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 28 | this case. Please refer to section 6 "Using BL31 entrypoint as the reset |
| 29 | address" for more information. |
| 30 | |
| 31 | Programmable CPU reset address |
| 32 | ------------------------------ |
| 33 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 34 | By default, TF-A assumes that the CPU reset address is not programmable. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 35 | Therefore, all CPUs start at the same address (typically address 0) whenever |
| 36 | they reset. Further logic is then required to identify whether it is a cold or |
| 37 | warm boot to direct CPUs to the right execution path. |
| 38 | |
| 39 | If the reset vector address (reflected in the reset vector base address register |
| 40 | ``RVBAR_EL3``) is programmable then it is possible to make each CPU start directly |
| 41 | at the right address, both on a cold and warm reset. Therefore, the boot type |
| 42 | detection can be skipped, resulting in the following boot flow: |
| 43 | |
| 44 | |Reset code flow with programmable reset address| |
| 45 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 46 | To enable this boot flow, compile TF-A with ``PROGRAMMABLE_RESET_ADDRESS=1``. |
| 47 | This option only affects the TF-A reset image, which is BL1 by default or BL31 if |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 48 | ``RESET_TO_BL31=1``. |
| 49 | |
| 50 | On both the FVP and Juno platforms, the reset vector address is not programmable |
| 51 | so both ports use ``PROGRAMMABLE_RESET_ADDRESS=0``. |
| 52 | |
| 53 | Cold boot on a single CPU |
| 54 | ------------------------- |
| 55 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 56 | By default, TF-A assumes that several CPUs may be released out of reset. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 57 | Therefore, the cold boot code has to arbitrate access to hardware resources |
| 58 | shared amongst CPUs. This is done by nominating one of the CPUs as the primary, |
| 59 | which is responsible for initialising shared hardware and coordinating the boot |
| 60 | flow with the other CPUs. |
| 61 | |
| 62 | If the platform guarantees that only a single CPU will ever be brought up then |
| 63 | no arbitration is required. The notion of primary/secondary CPU itself no longer |
| 64 | applies. This results in the following boot flow: |
| 65 | |
| 66 | |Reset code flow with single CPU released out of reset| |
| 67 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 68 | To enable this boot flow, compile TF-A with ``COLD_BOOT_SINGLE_CPU=1``. This |
| 69 | option only affects the TF-A reset image, which is BL1 by default or BL31 if |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 70 | ``RESET_TO_BL31=1``. |
| 71 | |
| 72 | On both the FVP and Juno platforms, although only one core is powered up by |
| 73 | default, there are platform-specific ways to release any number of cores out of |
| 74 | reset. Therefore, both platform ports use ``COLD_BOOT_SINGLE_CPU=0``. |
| 75 | |
| 76 | Programmable CPU reset address, Cold boot on a single CPU |
| 77 | --------------------------------------------------------- |
| 78 | |
| 79 | It is obviously possible to combine both optimisations on platforms that have |
| 80 | a programmable CPU reset address and which release a single CPU out of reset. |
| 81 | This results in the following boot flow: |
| 82 | |
| 83 | |
| 84 | |Reset code flow with programmable reset address and single CPU released out of reset| |
| 85 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 86 | To enable this boot flow, compile TF-A with both ``COLD_BOOT_SINGLE_CPU=1`` |
| 87 | and ``PROGRAMMABLE_RESET_ADDRESS=1``. These options only affect the TF-A reset |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 88 | image, which is BL1 by default or BL31 if ``RESET_TO_BL31=1``. |
| 89 | |
| 90 | Using BL31 entrypoint as the reset address |
| 91 | ------------------------------------------ |
| 92 | |
| 93 | On some platforms the runtime firmware (BL3x images) for the application |
| 94 | processors are loaded by some firmware running on a secure system processor |
| 95 | on the SoC, rather than by BL1 and BL2 running on the primary application |
| 96 | processor. For this type of SoC it is desirable for the application processor |
| 97 | to always reset to BL31 which eliminates the need for BL1 and BL2. |
| 98 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 99 | TF-A provides a build-time option ``RESET_TO_BL31`` that includes some additional |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 100 | logic in the BL31 entry point to support this use case. |
| 101 | |
| 102 | In this configuration, the platform's Trusted Boot Firmware must ensure that |
| 103 | BL31 is loaded to its runtime address, which must match the CPU's ``RVBAR_EL3`` |
| 104 | reset vector base address, before the application processor is powered on. |
| 105 | Additionally, platform software is responsible for loading the other BL3x images |
| 106 | required and providing entry point information for them to BL31. Loading these |
| 107 | images might be done by the Trusted Boot Firmware or by platform code in BL31. |
| 108 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 109 | Although the Arm FVP platform does not support programming the reset base |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 110 | address dynamically at run-time, it is possible to set the initial value of the |
| 111 | ``RVBAR_EL3`` register at start-up. This feature is provided on the Base FVP only. |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 112 | It allows the Arm FVP port to support the ``RESET_TO_BL31`` configuration, in |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 113 | which case the ``bl31.bin`` image must be loaded to its run address in Trusted |
| 114 | SRAM and all CPU reset vectors be changed from the default ``0x0`` to this run |
| 115 | address. See the `User Guide`_ for details of running the FVP models in this way. |
| 116 | |
| 117 | Although technically it would be possible to program the reset base address with |
| 118 | the right support in the SCP firmware, this is currently not implemented so the |
| 119 | Juno port doesn't support the ``RESET_TO_BL31`` configuration. |
| 120 | |
| 121 | The ``RESET_TO_BL31`` configuration requires some additions and changes in the |
| 122 | BL31 functionality: |
| 123 | |
| 124 | Determination of boot path |
| 125 | ~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 126 | |
| 127 | In this configuration, BL31 uses the same reset framework and code as the one |
| 128 | described for BL1 above. Therefore, it is affected by the |
| 129 | ``PROGRAMMABLE_RESET_ADDRESS`` and ``COLD_BOOT_SINGLE_CPU`` build options in the |
| 130 | same way. |
| 131 | |
| 132 | In the default, unoptimised BL31 reset flow, on a warm boot a CPU is directed |
| 133 | to the PSCI implementation via a platform defined mechanism. On a cold boot, |
| 134 | the platform must place any secondary CPUs into a safe state while the primary |
| 135 | CPU executes a modified BL31 initialization, as described below. |
| 136 | |
| 137 | Platform initialization |
| 138 | ~~~~~~~~~~~~~~~~~~~~~~~ |
| 139 | |
| 140 | In this configuration, when the CPU resets to BL31 there are no parameters that |
| 141 | can be passed in registers by previous boot stages. Instead, the platform code |
| 142 | in BL31 needs to know, or be able to determine, the location of the BL32 (if |
| 143 | required) and BL33 images and provide this information in response to the |
| 144 | ``bl31_plat_get_next_image_ep_info()`` function. |
| 145 | |
| 146 | Additionally, platform software is responsible for carrying out any security |
| 147 | initialisation, for example programming a TrustZone address space controller. |
| 148 | This might be done by the Trusted Boot Firmware or by platform code in BL31. |
| 149 | |
| 150 | -------------- |
| 151 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 152 | *Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved.* |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 153 | |
| 154 | .. _Firmware Design: firmware-design.rst |
Paul Beesley | ea22512 | 2019-02-11 17:54:45 +0000 | [diff] [blame] | 155 | .. _User Guide: ../getting_started/user-guide.rst |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 156 | |
Paul Beesley | ea22512 | 2019-02-11 17:54:45 +0000 | [diff] [blame] | 157 | .. |Default reset code flow| image:: ../diagrams/default_reset_code.png?raw=true |
| 158 | .. |Reset code flow with programmable reset address| image:: ../diagrams/reset_code_no_boot_type_check.png?raw=true |
| 159 | .. |Reset code flow with single CPU released out of reset| image:: ../diagrams/reset_code_no_cpu_check.png?raw=true |
| 160 | .. |Reset code flow with programmable reset address and single CPU released out of reset| image:: ../diagrams/reset_code_no_checks.png?raw=true |