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Tony Xief6118cc2016-01-15 17:17:32 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
Antonio Nino Diaz493bf332016-12-14 14:31:32 +000014 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
Tony Xief6118cc2016-01-15 17:17:32 +080018 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <asm_macros.S>
33#include <platform_def.h>
34#include <pmu_sram.h>
35
36 .globl pmu_cpuson_entrypoint_start
37 .globl pmu_cpuson_entrypoint_end
38
39func pmu_cpuson_entrypoint
40pmu_cpuson_entrypoint_start:
41 ldr x5, psram_data
Tony Xief6118cc2016-01-15 17:17:32 +080042check_wake_cpus:
43 mrs x0, MPIDR_EL1
44 and x1, x0, #MPIDR_CPU_MASK
45 and x0, x0, #MPIDR_CLUSTER_MASK
46 orr x0, x0, x1
47 /* primary_cpu */
48 ldr w1, [x5, #PSRAM_DT_MPIDR]
49 cmp w0, w1
50 b.eq sys_wakeup
51 /*
52 * If the core is not the primary cpu,
53 * force the core into wfe.
54 */
55wfe_loop:
56 wfe
57 b wfe_loop
58sys_wakeup:
59 /* check ddr flag for resume ddr */
60 ldr w2, [x5, #PSRAM_DT_DDRFLAG]
61 cmp w2, #0x0
62 b.eq sys_resume
63ddr_resume:
64 ldr x2, [x5, #PSRAM_DT_SP]
65 mov sp, x2
66 ldr x1, [x5, #PSRAM_DT_DDR_FUNC]
67 ldr x0, [x5, #PSRAM_DT_DDR_DATA]
68 blr x1
69sys_resume:
70 ldr x1, sys_wakeup_entry
71 br x1
72
73 .align 3
74psram_data:
75 .quad PSRAM_DT_BASE
Tony Xief6118cc2016-01-15 17:17:32 +080076sys_wakeup_entry:
77 .quad psci_entrypoint
Tony Xief6118cc2016-01-15 17:17:32 +080078pmu_cpuson_entrypoint_end:
79 .word 0
80endfunc pmu_cpuson_entrypoint