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git01.mediatek.com / filogic / atf / 492e2459558bb3e167c01fcd497cf5028f264396 / . / lib / cpus / aarch64 / cortex_a73.S
blob: 0a961ea3336bed7edd66b7014e264f9899a75640 [file] [log] [blame]
Yatharth Kochar63af6872016-02-09 12:00:03 +0000[diff] [blame]1/*
Dimitris Papastamos858bd612018-01-16 10:32:47 +0000[diff] [blame]2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Yatharth Kochar63af6872016-02-09 12:00:03 +0000[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Yatharth Kochar63af6872016-02-09 12:00:03 +0000[diff] [blame]5 */
6#include <arch.h>
7#include <asm_macros.S>
8#include <bl_common.h>
9#include <cortex_a73.h>
10#include <cpu_macros.S>
11#include <plat_macros.S>
12
13 /* ---------------------------------------------
14 * Disable L1 data cache
15 * ---------------------------------------------
16 */
17func cortex_a73_disable_dcache
18 mrs x1, sctlr_el3
19 bic x1, x1, #SCTLR_C_BIT
20 msr sctlr_el3, x1
21 isb
22 ret
23endfunc cortex_a73_disable_dcache
24
25 /* ---------------------------------------------
26 * Disable intra-cluster coherency
27 * ---------------------------------------------
28 */
29func cortex_a73_disable_smp
30 mrs x0, CORTEX_A73_CPUECTLR_EL1
31 bic x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
32 msr CORTEX_A73_CPUECTLR_EL1, x0
33 isb
34 dsb sy
35 ret
36endfunc cortex_a73_disable_smp
37
38func cortex_a73_reset_func
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000[diff] [blame]39#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
Dimitris Papastamos780cc952018-03-12 13:27:02 +0000[diff] [blame]40 cpu_check_csv2 x0, 1f
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000[diff] [blame]41 adr x0, workaround_bpiall_vbar0_runtime_exceptions
42 msr vbar_el3, x0
Dimitris Papastamos780cc952018-03-12 13:27:02 +0000[diff] [blame]431:
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000[diff] [blame]44#endif
45
Yatharth Kochar63af6872016-02-09 12:00:03 +0000[diff] [blame]46 /* ---------------------------------------------
47 * Enable the SMP bit.
48 * Clobbers : x0
49 * ---------------------------------------------
50 */
51 mrs x0, CORTEX_A73_CPUECTLR_EL1
52 orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
53 msr CORTEX_A73_CPUECTLR_EL1, x0
54 isb
55 ret
56endfunc cortex_a73_reset_func
57
58func cortex_a73_core_pwr_dwn
59 mov x18, x30
60
61 /* ---------------------------------------------
62 * Turn off caches.
63 * ---------------------------------------------
64 */
65 bl cortex_a73_disable_dcache
66
67 /* ---------------------------------------------
68 * Flush L1 caches.
69 * ---------------------------------------------
70 */
71 mov x0, #DCCISW
72 bl dcsw_op_level1
73
74 /* ---------------------------------------------
75 * Come out of intra cluster coherency
76 * ---------------------------------------------
77 */
78 mov x30, x18
79 b cortex_a73_disable_smp
80endfunc cortex_a73_core_pwr_dwn
81
82func cortex_a73_cluster_pwr_dwn
83 mov x18, x30
84
85 /* ---------------------------------------------
86 * Turn off caches.
87 * ---------------------------------------------
88 */
89 bl cortex_a73_disable_dcache
90
91 /* ---------------------------------------------
92 * Flush L1 caches.
93 * ---------------------------------------------
94 */
95 mov x0, #DCCISW
96 bl dcsw_op_level1
97
98 /* ---------------------------------------------
99 * Disable the optional ACP.
100 * ---------------------------------------------
101 */
102 bl plat_disable_acp
103
104 /* ---------------------------------------------
105 * Flush L2 caches.
106 * ---------------------------------------------
107 */
108 mov x0, #DCCISW
109 bl dcsw_op_level2
110
111 /* ---------------------------------------------
112 * Come out of intra cluster coherency
113 * ---------------------------------------------
114 */
115 mov x30, x18
116 b cortex_a73_disable_smp
117endfunc cortex_a73_cluster_pwr_dwn
118
Dimitris Papastamos858bd612018-01-16 10:32:47 +0000[diff] [blame]119func check_errata_cve_2017_5715
Dimitris Papastamos780cc952018-03-12 13:27:02 +0000[diff] [blame]120 cpu_check_csv2 x0, 1f
Dimitris Papastamos858bd612018-01-16 10:32:47 +0000[diff] [blame]121#if WORKAROUND_CVE_2017_5715
122 mov x0, #ERRATA_APPLIES
123#else
124 mov x0, #ERRATA_MISSING
125#endif
126 ret
Dimitris Papastamos780cc952018-03-12 13:27:02 +0000[diff] [blame]1271:
128 mov x0, #ERRATA_NOT_APPLIES
129 ret
Dimitris Papastamos858bd612018-01-16 10:32:47 +0000[diff] [blame]130endfunc check_errata_cve_2017_5715
131
132#if REPORT_ERRATA
133/*
134 * Errata printing function for Cortex A75. Must follow AAPCS.
135 */
136func cortex_a73_errata_report
137 stp x8, x30, [sp, #-16]!
138
139 bl cpu_get_rev_var
140 mov x8, x0
141
142 /*
143 * Report all errata. The revision-variant information is passed to
144 * checking functions of each errata.
145 */
146 report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715
147
148 ldp x8, x30, [sp], #16
149 ret
150endfunc cortex_a73_errata_report
151#endif
152
Yatharth Kochar63af6872016-02-09 12:00:03 +0000[diff] [blame]153 /* ---------------------------------------------
154 * This function provides cortex_a73 specific
155 * register information for crash reporting.
156 * It needs to return with x6 pointing to
157 * a list of register names in ascii and
158 * x8 - x15 having values of registers to be
159 * reported.
160 * ---------------------------------------------
161 */
162.section .rodata.cortex_a73_regs, "aS"
163cortex_a73_regs: /* The ascii list of register names to be reported */
Naga Sureshkumar Relli6a72a912016-07-01 12:52:41 +0530[diff] [blame]164 .asciz "cpuectlr_el1", "l2merrsr_el1", ""
Yatharth Kochar63af6872016-02-09 12:00:03 +0000[diff] [blame]165
166func cortex_a73_cpu_reg_dump
167 adr x6, cortex_a73_regs
168 mrs x8, CORTEX_A73_CPUECTLR_EL1
Naga Sureshkumar Relli6a72a912016-07-01 12:52:41 +0530[diff] [blame]169 mrs x9, CORTEX_A73_L2MERRSR_EL1
Yatharth Kochar63af6872016-02-09 12:00:03 +0000[diff] [blame]170 ret
171endfunc cortex_a73_cpu_reg_dump
172
Dimitris Papastamos914757c2018-03-12 14:47:09 +0000[diff] [blame]173declare_cpu_ops_workaround_cve_2017_5715 cortex_a73, CORTEX_A73_MIDR, \
Jeenu Viswambharanee5eb802016-11-18 12:58:28 +0000[diff] [blame]174 cortex_a73_reset_func, \
Dimitris Papastamos914757c2018-03-12 14:47:09 +0000[diff] [blame]175 check_errata_cve_2017_5715, \
Jeenu Viswambharanee5eb802016-11-18 12:58:28 +0000[diff] [blame]176 cortex_a73_core_pwr_dwn, \
177 cortex_a73_cluster_pwr_dwn