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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Soby Mathew981487a2015-07-13 14:10:57 +01002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley2bd4ef22014-04-09 13:14:54 +010031#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <assert.h>
34#include <bl_common.h>
35#include <context.h>
Jeenu Viswambharancaa84932014-02-06 10:36:15 +000036#include <context_mgmt.h>
Dan Handley714a0d22014-04-09 13:13:04 +010037#include <debug.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010038#include <platform.h>
Andrew Thoelke4e126072014-06-04 21:10:52 +010039#include <string.h>
Dan Handley714a0d22014-04-09 13:13:04 +010040#include "psci_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010041
Achin Gupta607084e2014-02-09 18:24:19 +000042/*
Jeenu Viswambharan7f366602014-02-20 17:11:00 +000043 * SPD power management operations, expected to be supplied by the registered
44 * SPD on successful SP initialization
Achin Gupta607084e2014-02-09 18:24:19 +000045 */
Dan Handleye2712bc2014-04-10 15:37:22 +010046const spd_pm_ops_t *psci_spd_pm;
Achin Gupta607084e2014-02-09 18:24:19 +000047
Soby Mathew981487a2015-07-13 14:10:57 +010048/*
49 * PSCI requested local power state map. This array is used to store the local
50 * power states requested by a CPU for power levels from level 1 to
51 * PLAT_MAX_PWR_LVL. It does not store the requested local power state for power
52 * level 0 (PSCI_CPU_PWR_LVL) as the requested and the target power state for a
53 * CPU are the same.
54 *
55 * During state coordination, the platform is passed an array containing the
56 * local states requested for a particular non cpu power domain by each cpu
57 * within the domain.
58 *
59 * TODO: Dense packing of the requested states will cause cache thrashing
60 * when multiple power domains write to it. If we allocate the requested
61 * states at each power level in a cache-line aligned per-domain memory,
62 * the cache thrashing can be avoided.
63 */
64static plat_local_state_t
65 psci_req_local_pwr_states[PLAT_MAX_PWR_LVL][PLATFORM_CORE_COUNT];
66
67
Achin Gupta4f6ad662013-10-25 09:08:21 +010068/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +010069 * Arrays that hold the platform's power domain tree information for state
70 * management of power domains.
71 * Each node in the array 'psci_non_cpu_pd_nodes' corresponds to a power domain
72 * which is an ancestor of a CPU power domain.
73 * Each node in the array 'psci_cpu_pd_nodes' corresponds to a cpu power domain
Achin Gupta4f6ad662013-10-25 09:08:21 +010074 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +010075non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]
Soby Mathew2ae20432015-01-08 18:02:44 +000076#if USE_COHERENT_MEM
Soren Brinkmann46dd1702016-01-14 10:11:05 -080077__section("tzfw_coherent_mem")
Soby Mathew2ae20432015-01-08 18:02:44 +000078#endif
79;
Achin Gupta4f6ad662013-10-25 09:08:21 +010080
Andrew Thoelkee466c9f2015-09-10 11:39:36 +010081DEFINE_BAKERY_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]);
82
Soby Mathew981487a2015-07-13 14:10:57 +010083cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT];
84
Achin Gupta4f6ad662013-10-25 09:08:21 +010085/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +010086 * Pointer to functions exported by the platform to complete power mgmt. ops
87 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +010088const plat_psci_ops_t *psci_plat_pm_ops;
Achin Gupta4f6ad662013-10-25 09:08:21 +010089
Soby Mathew981487a2015-07-13 14:10:57 +010090/******************************************************************************
91 * Check that the maximum power level supported by the platform makes sense
92 *****************************************************************************/
93CASSERT(PLAT_MAX_PWR_LVL <= PSCI_MAX_PWR_LVL && \
94 PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL, \
95 assert_platform_max_pwrlvl_check);
Soby Mathew2b7de2b2015-02-12 14:45:02 +000096
Soby Mathew981487a2015-07-13 14:10:57 +010097/*
98 * The plat_local_state used by the platform is one of these types: RUN,
99 * RETENTION and OFF. The platform can define further sub-states for each type
100 * apart from RUN. This categorization is done to verify the sanity of the
101 * psci_power_state passed by the platform and to print debug information. The
102 * categorization is done on the basis of the following conditions:
103 *
104 * 1. If (plat_local_state == 0) then the category is STATE_TYPE_RUN.
105 *
106 * 2. If (0 < plat_local_state <= PLAT_MAX_RET_STATE), then the category is
107 * STATE_TYPE_RETN.
108 *
109 * 3. If (plat_local_state > PLAT_MAX_RET_STATE), then the category is
110 * STATE_TYPE_OFF.
111 */
112typedef enum plat_local_state_type {
113 STATE_TYPE_RUN = 0,
114 STATE_TYPE_RETN,
115 STATE_TYPE_OFF
116} plat_local_state_type_t;
117
118/* The macro used to categorize plat_local_state. */
119#define find_local_state_type(plat_local_state) \
120 ((plat_local_state) ? ((plat_local_state > PLAT_MAX_RET_STATE) \
121 ? STATE_TYPE_OFF : STATE_TYPE_RETN) \
122 : STATE_TYPE_RUN)
123
124/******************************************************************************
125 * Check that the maximum retention level supported by the platform is less
126 * than the maximum off level.
127 *****************************************************************************/
128CASSERT(PLAT_MAX_RET_STATE < PLAT_MAX_OFF_STATE, \
129 assert_platform_max_off_and_retn_state_check);
130
131/******************************************************************************
132 * This function ensures that the power state parameter in a CPU_SUSPEND request
133 * is valid. If so, it returns the requested states for each power level.
134 *****************************************************************************/
135int psci_validate_power_state(unsigned int power_state,
136 psci_power_state_t *state_info)
Achin Guptaf6b9e992014-07-31 11:19:11 +0100137{
Soby Mathew981487a2015-07-13 14:10:57 +0100138 /* Check SBZ bits in power state are zero */
139 if (psci_check_power_state(power_state))
140 return PSCI_E_INVALID_PARAMS;
Achin Guptaf6b9e992014-07-31 11:19:11 +0100141
Soby Mathew981487a2015-07-13 14:10:57 +0100142 assert(psci_plat_pm_ops->validate_power_state);
Achin Guptaf6b9e992014-07-31 11:19:11 +0100143
Soby Mathew981487a2015-07-13 14:10:57 +0100144 /* Validate the power_state using platform pm_ops */
145 return psci_plat_pm_ops->validate_power_state(power_state, state_info);
146}
Achin Guptaf6b9e992014-07-31 11:19:11 +0100147
Soby Mathew981487a2015-07-13 14:10:57 +0100148/******************************************************************************
149 * This function retrieves the `psci_power_state_t` for system suspend from
150 * the platform.
151 *****************************************************************************/
152void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info)
153{
154 /*
155 * Assert that the required pm_ops hook is implemented to ensure that
156 * the capability detected during psci_setup() is valid.
157 */
158 assert(psci_plat_pm_ops->get_sys_suspend_power_state);
159
160 /*
161 * Query the platform for the power_state required for system suspend
162 */
163 psci_plat_pm_ops->get_sys_suspend_power_state(state_info);
Achin Guptaf6b9e992014-07-31 11:19:11 +0100164}
165
166/*******************************************************************************
Soby Mathew96168382014-12-17 14:47:57 +0000167 * This function verifies that the all the other cores in the system have been
168 * turned OFF and the current CPU is the last running CPU in the system.
169 * Returns 1 (true) if the current CPU is the last ON CPU or 0 (false)
170 * otherwise.
171 ******************************************************************************/
172unsigned int psci_is_last_on_cpu(void)
173{
Soby Mathew981487a2015-07-13 14:10:57 +0100174 unsigned int cpu_idx, my_idx = plat_my_core_pos();
Soby Mathew96168382014-12-17 14:47:57 +0000175
Soby Mathew981487a2015-07-13 14:10:57 +0100176 for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) {
177 if (cpu_idx == my_idx) {
178 assert(psci_get_aff_info_state() == AFF_STATE_ON);
Soby Mathew96168382014-12-17 14:47:57 +0000179 continue;
180 }
181
Soby Mathew981487a2015-07-13 14:10:57 +0100182 if (psci_get_aff_info_state_by_idx(cpu_idx) != AFF_STATE_OFF)
Soby Mathew96168382014-12-17 14:47:57 +0000183 return 0;
184 }
185
186 return 1;
187}
188
189/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100190 * Routine to return the maximum power level to traverse to after a cpu has
191 * been physically powered up. It is expected to be called immediately after
192 * reset from assembler code.
Achin Guptaf6b9e992014-07-31 11:19:11 +0100193 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100194static unsigned int get_power_on_target_pwrlvl(void)
Achin Guptaf6b9e992014-07-31 11:19:11 +0100195{
Soby Mathew011ca182015-07-29 17:05:03 +0100196 unsigned int pwrlvl;
Achin Guptaf6b9e992014-07-31 11:19:11 +0100197
198 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100199 * Assume that this cpu was suspended and retrieve its target power
200 * level. If it is invalid then it could only have been turned off
201 * earlier. PLAT_MAX_PWR_LVL will be the highest power level a
202 * cpu can be turned off to.
Achin Guptaf6b9e992014-07-31 11:19:11 +0100203 */
Soby Mathew981487a2015-07-13 14:10:57 +0100204 pwrlvl = psci_get_suspend_pwrlvl();
Soby Mathew011ca182015-07-29 17:05:03 +0100205 if (pwrlvl == PSCI_INVALID_PWR_LVL)
Soby Mathew981487a2015-07-13 14:10:57 +0100206 pwrlvl = PLAT_MAX_PWR_LVL;
207 return pwrlvl;
Achin Guptaf6b9e992014-07-31 11:19:11 +0100208}
209
Soby Mathew981487a2015-07-13 14:10:57 +0100210/******************************************************************************
211 * Helper function to update the requested local power state array. This array
212 * does not store the requested state for the CPU power level. Hence an
213 * assertion is added to prevent us from accessing the wrong index.
214 *****************************************************************************/
215static void psci_set_req_local_pwr_state(unsigned int pwrlvl,
216 unsigned int cpu_idx,
217 plat_local_state_t req_pwr_state)
Achin Guptaf6b9e992014-07-31 11:19:11 +0100218{
Soby Mathew981487a2015-07-13 14:10:57 +0100219 assert(pwrlvl > PSCI_CPU_PWR_LVL);
220 psci_req_local_pwr_states[pwrlvl - 1][cpu_idx] = req_pwr_state;
Achin Guptaf6b9e992014-07-31 11:19:11 +0100221}
222
Soby Mathew981487a2015-07-13 14:10:57 +0100223/******************************************************************************
224 * This function initializes the psci_req_local_pwr_states.
225 *****************************************************************************/
226void psci_init_req_local_pwr_states(void)
Achin Guptaa45e3972013-12-05 15:10:48 +0000227{
Soby Mathew981487a2015-07-13 14:10:57 +0100228 /* Initialize the requested state of all non CPU power domains as OFF */
229 memset(&psci_req_local_pwr_states, PLAT_MAX_OFF_STATE,
230 sizeof(psci_req_local_pwr_states));
231}
Achin Guptaa45e3972013-12-05 15:10:48 +0000232
Soby Mathew981487a2015-07-13 14:10:57 +0100233/******************************************************************************
234 * Helper function to return a reference to an array containing the local power
235 * states requested by each cpu for a power domain at 'pwrlvl'. The size of the
236 * array will be the number of cpu power domains of which this power domain is
237 * an ancestor. These requested states will be used to determine a suitable
238 * target state for this power domain during psci state coordination. An
239 * assertion is added to prevent us from accessing the CPU power level.
240 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100241static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl,
242 unsigned int cpu_idx)
Soby Mathew981487a2015-07-13 14:10:57 +0100243{
244 assert(pwrlvl > PSCI_CPU_PWR_LVL);
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100245
Soby Mathew981487a2015-07-13 14:10:57 +0100246 return &psci_req_local_pwr_states[pwrlvl - 1][cpu_idx];
247}
Achin Guptaa45e3972013-12-05 15:10:48 +0000248
Soby Mathew981487a2015-07-13 14:10:57 +0100249/******************************************************************************
250 * Helper function to return the current local power state of each power domain
251 * from the current cpu power domain to its ancestor at the 'end_pwrlvl'. This
252 * function will be called after a cpu is powered on to find the local state
253 * each power domain has emerged from.
254 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100255static void psci_get_target_local_pwr_states(unsigned int end_pwrlvl,
Soby Mathew981487a2015-07-13 14:10:57 +0100256 psci_power_state_t *target_state)
257{
Soby Mathew011ca182015-07-29 17:05:03 +0100258 unsigned int parent_idx, lvl;
Soby Mathew981487a2015-07-13 14:10:57 +0100259 plat_local_state_t *pd_state = target_state->pwr_domain_state;
260
261 pd_state[PSCI_CPU_PWR_LVL] = psci_get_cpu_local_state();
262 parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node;
263
264 /* Copy the local power state from node to state_info */
265 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) {
266#if !USE_COHERENT_MEM
267 /*
268 * If using normal memory for psci_non_cpu_pd_nodes, we need
269 * to flush before reading the local power state as another
270 * cpu in the same power domain could have updated it and this
271 * code runs before caches are enabled.
272 */
273 flush_dcache_range(
Soby Mathew011ca182015-07-29 17:05:03 +0100274 (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx],
Soby Mathew981487a2015-07-13 14:10:57 +0100275 sizeof(psci_non_cpu_pd_nodes[parent_idx]));
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100276#endif
Soby Mathew981487a2015-07-13 14:10:57 +0100277 pd_state[lvl] = psci_non_cpu_pd_nodes[parent_idx].local_state;
278 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
279 }
280
281 /* Set the the higher levels to RUN */
282 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++)
283 target_state->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN;
284}
285
286/******************************************************************************
287 * Helper function to set the target local power state that each power domain
288 * from the current cpu power domain to its ancestor at the 'end_pwrlvl' will
289 * enter. This function will be called after coordination of requested power
290 * states has been done for each power level.
291 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100292static void psci_set_target_local_pwr_states(unsigned int end_pwrlvl,
Soby Mathew981487a2015-07-13 14:10:57 +0100293 const psci_power_state_t *target_state)
294{
Soby Mathew011ca182015-07-29 17:05:03 +0100295 unsigned int parent_idx, lvl;
Soby Mathew981487a2015-07-13 14:10:57 +0100296 const plat_local_state_t *pd_state = target_state->pwr_domain_state;
297
298 psci_set_cpu_local_state(pd_state[PSCI_CPU_PWR_LVL]);
Achin Guptaa45e3972013-12-05 15:10:48 +0000299
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100300 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100301 * Need to flush as local_state will be accessed with Data Cache
302 * disabled during power on
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100303 */
Soby Mathew981487a2015-07-13 14:10:57 +0100304 flush_cpu_data(psci_svc_cpu_data.local_state);
305
306 parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node;
307
308 /* Copy the local_state from state_info */
309 for (lvl = 1; lvl <= end_pwrlvl; lvl++) {
310 psci_non_cpu_pd_nodes[parent_idx].local_state = pd_state[lvl];
311#if !USE_COHERENT_MEM
312 flush_dcache_range(
Soby Mathew011ca182015-07-29 17:05:03 +0100313 (uintptr_t)&psci_non_cpu_pd_nodes[parent_idx],
314 sizeof(psci_non_cpu_pd_nodes[parent_idx]));
Soby Mathew981487a2015-07-13 14:10:57 +0100315#endif
316 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
317 }
Achin Guptaa45e3972013-12-05 15:10:48 +0000318}
319
Soby Mathew981487a2015-07-13 14:10:57 +0100320
Achin Guptaa45e3972013-12-05 15:10:48 +0000321/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100322 * PSCI helper function to get the parent nodes corresponding to a cpu_index.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100323 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +0100324void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx,
Soby Mathew011ca182015-07-29 17:05:03 +0100325 unsigned int end_lvl,
Soby Mathew981487a2015-07-13 14:10:57 +0100326 unsigned int node_index[])
327{
328 unsigned int parent_node = psci_cpu_pd_nodes[cpu_idx].parent_node;
329 int i;
330
331 for (i = PSCI_CPU_PWR_LVL + 1; i <= end_lvl; i++) {
332 *node_index++ = parent_node;
333 parent_node = psci_non_cpu_pd_nodes[parent_node].parent_node;
334 }
335}
336
337/******************************************************************************
338 * This function is invoked post CPU power up and initialization. It sets the
339 * affinity info state, target power state and requested power state for the
340 * current CPU and all its ancestor power domains to RUN.
341 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100342void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl)
Soby Mathew981487a2015-07-13 14:10:57 +0100343{
Soby Mathew011ca182015-07-29 17:05:03 +0100344 unsigned int parent_idx, cpu_idx = plat_my_core_pos(), lvl;
Soby Mathew981487a2015-07-13 14:10:57 +0100345 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
346
347 /* Reset the local_state to RUN for the non cpu power domains. */
348 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) {
349 psci_non_cpu_pd_nodes[parent_idx].local_state =
350 PSCI_LOCAL_STATE_RUN;
351#if !USE_COHERENT_MEM
352 flush_dcache_range(
Soby Mathew011ca182015-07-29 17:05:03 +0100353 (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx],
Soby Mathew981487a2015-07-13 14:10:57 +0100354 sizeof(psci_non_cpu_pd_nodes[parent_idx]));
355#endif
356 psci_set_req_local_pwr_state(lvl,
357 cpu_idx,
358 PSCI_LOCAL_STATE_RUN);
359 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
360 }
361
362 /* Set the affinity info state to ON */
363 psci_set_aff_info_state(AFF_STATE_ON);
364
365 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN);
366 flush_cpu_data(psci_svc_cpu_data);
367}
368
369/******************************************************************************
370 * This function is passed the local power states requested for each power
371 * domain (state_info) between the current CPU domain and its ancestors until
372 * the target power level (end_pwrlvl). It updates the array of requested power
373 * states with this information.
374 *
375 * Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it
376 * retrieves the states requested by all the cpus of which the power domain at
377 * that level is an ancestor. It passes this information to the platform to
378 * coordinate and return the target power state. If the target state for a level
379 * is RUN then subsequent levels are not considered. At the CPU level, state
380 * coordination is not required. Hence, the requested and the target states are
381 * the same.
382 *
383 * The 'state_info' is updated with the target state for each level between the
384 * CPU and the 'end_pwrlvl' and returned to the caller.
385 *
386 * This function will only be invoked with data cache enabled and while
387 * powering down a core.
388 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100389void psci_do_state_coordination(unsigned int end_pwrlvl,
390 psci_power_state_t *state_info)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100391{
Soby Mathew981487a2015-07-13 14:10:57 +0100392 unsigned int lvl, parent_idx, cpu_idx = plat_my_core_pos();
393 unsigned int start_idx, ncpus;
394 plat_local_state_t target_state, *req_states;
395
Soby Mathew1298e692016-02-02 14:23:10 +0000396 assert(end_pwrlvl <= PLAT_MAX_PWR_LVL);
Soby Mathew981487a2015-07-13 14:10:57 +0100397 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
398
399 /* For level 0, the requested state will be equivalent
400 to target state */
401 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) {
402
403 /* First update the requested power state */
404 psci_set_req_local_pwr_state(lvl, cpu_idx,
405 state_info->pwr_domain_state[lvl]);
406
407 /* Get the requested power states for this power level */
408 start_idx = psci_non_cpu_pd_nodes[parent_idx].cpu_start_idx;
409 req_states = psci_get_req_local_pwr_states(lvl, start_idx);
410
411 /*
412 * Let the platform coordinate amongst the requested states at
413 * this power level and return the target local power state.
414 */
415 ncpus = psci_non_cpu_pd_nodes[parent_idx].ncpus;
416 target_state = plat_get_target_pwr_state(lvl,
417 req_states,
418 ncpus);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100419
Soby Mathew981487a2015-07-13 14:10:57 +0100420 state_info->pwr_domain_state[lvl] = target_state;
421
422 /* Break early if the negotiated target power state is RUN */
423 if (is_local_state_run(state_info->pwr_domain_state[lvl]))
424 break;
425
426 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
427 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100428
429 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100430 * This is for cases when we break out of the above loop early because
431 * the target power state is RUN at a power level < end_pwlvl.
432 * We update the requested power state from state_info and then
433 * set the target state as RUN.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100434 */
Soby Mathew981487a2015-07-13 14:10:57 +0100435 for (lvl = lvl + 1; lvl <= end_pwrlvl; lvl++) {
436 psci_set_req_local_pwr_state(lvl, cpu_idx,
437 state_info->pwr_domain_state[lvl]);
438 state_info->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100439
Soby Mathew981487a2015-07-13 14:10:57 +0100440 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100441
Soby Mathew981487a2015-07-13 14:10:57 +0100442 /* Update the target state in the power domain nodes */
443 psci_set_target_local_pwr_states(end_pwrlvl, state_info);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100444}
445
Soby Mathew981487a2015-07-13 14:10:57 +0100446/******************************************************************************
447 * This function validates a suspend request by making sure that if a standby
448 * state is requested then no power level is turned off and the highest power
449 * level is placed in a standby/retention state.
450 *
451 * It also ensures that the state level X will enter is not shallower than the
452 * state level X + 1 will enter.
453 *
454 * This validation will be enabled only for DEBUG builds as the platform is
455 * expected to perform these validations as well.
456 *****************************************************************************/
457int psci_validate_suspend_req(const psci_power_state_t *state_info,
458 unsigned int is_power_down_state)
Achin Gupta0959db52013-12-02 17:33:04 +0000459{
Soby Mathew981487a2015-07-13 14:10:57 +0100460 unsigned int max_off_lvl, target_lvl, max_retn_lvl;
461 plat_local_state_t state;
462 plat_local_state_type_t req_state_type, deepest_state_type;
463 int i;
Achin Gupta0959db52013-12-02 17:33:04 +0000464
Soby Mathew981487a2015-07-13 14:10:57 +0100465 /* Find the target suspend power level */
466 target_lvl = psci_find_target_suspend_lvl(state_info);
Soby Mathew011ca182015-07-29 17:05:03 +0100467 if (target_lvl == PSCI_INVALID_PWR_LVL)
Achin Gupta0959db52013-12-02 17:33:04 +0000468 return PSCI_E_INVALID_PARAMS;
469
Soby Mathew981487a2015-07-13 14:10:57 +0100470 /* All power domain levels are in a RUN state to begin with */
471 deepest_state_type = STATE_TYPE_RUN;
472
473 for (i = target_lvl; i >= PSCI_CPU_PWR_LVL; i--) {
474 state = state_info->pwr_domain_state[i];
475 req_state_type = find_local_state_type(state);
476
477 /*
478 * While traversing from the highest power level to the lowest,
479 * the state requested for lower levels has to be the same or
480 * deeper i.e. equal to or greater than the state at the higher
481 * levels. If this condition is true, then the requested state
482 * becomes the deepest state encountered so far.
483 */
484 if (req_state_type < deepest_state_type)
485 return PSCI_E_INVALID_PARAMS;
486 deepest_state_type = req_state_type;
487 }
488
489 /* Find the highest off power level */
490 max_off_lvl = psci_find_max_off_lvl(state_info);
491
492 /* The target_lvl is either equal to the max_off_lvl or max_retn_lvl */
Soby Mathew011ca182015-07-29 17:05:03 +0100493 max_retn_lvl = PSCI_INVALID_PWR_LVL;
Soby Mathew981487a2015-07-13 14:10:57 +0100494 if (target_lvl != max_off_lvl)
495 max_retn_lvl = target_lvl;
496
497 /*
498 * If this is not a request for a power down state then max off level
499 * has to be invalid and max retention level has to be a valid power
500 * level.
501 */
Soby Mathew011ca182015-07-29 17:05:03 +0100502 if (!is_power_down_state && (max_off_lvl != PSCI_INVALID_PWR_LVL ||
503 max_retn_lvl == PSCI_INVALID_PWR_LVL))
Achin Gupta0959db52013-12-02 17:33:04 +0000504 return PSCI_E_INVALID_PARAMS;
505
506 return PSCI_E_SUCCESS;
507}
508
Soby Mathew981487a2015-07-13 14:10:57 +0100509/******************************************************************************
510 * This function finds the highest power level which will be powered down
511 * amongst all the power levels specified in the 'state_info' structure
512 *****************************************************************************/
513unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info)
Achin Guptacab78e42014-07-28 00:09:01 +0100514{
Soby Mathew981487a2015-07-13 14:10:57 +0100515 int i;
Achin Guptacab78e42014-07-28 00:09:01 +0100516
Soby Mathew981487a2015-07-13 14:10:57 +0100517 for (i = PLAT_MAX_PWR_LVL; i >= PSCI_CPU_PWR_LVL; i--) {
518 if (is_local_state_off(state_info->pwr_domain_state[i]))
519 return i;
520 }
521
Soby Mathew011ca182015-07-29 17:05:03 +0100522 return PSCI_INVALID_PWR_LVL;
Soby Mathew981487a2015-07-13 14:10:57 +0100523}
524
525/******************************************************************************
526 * This functions finds the level of the highest power domain which will be
527 * placed in a low power state during a suspend operation.
528 *****************************************************************************/
529unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info)
530{
531 int i;
532
533 for (i = PLAT_MAX_PWR_LVL; i >= PSCI_CPU_PWR_LVL; i--) {
534 if (!is_local_state_run(state_info->pwr_domain_state[i]))
535 return i;
Achin Guptacab78e42014-07-28 00:09:01 +0100536 }
Soby Mathew981487a2015-07-13 14:10:57 +0100537
Soby Mathew011ca182015-07-29 17:05:03 +0100538 return PSCI_INVALID_PWR_LVL;
Achin Guptacab78e42014-07-28 00:09:01 +0100539}
540
541/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100542 * This function is passed a cpu_index and the highest level in the topology
543 * tree that the operation should be applied to. It picks up locks in order of
544 * increasing power domain level in the range specified.
Achin Gupta0959db52013-12-02 17:33:04 +0000545 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100546void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl,
547 unsigned int cpu_idx)
Achin Gupta0959db52013-12-02 17:33:04 +0000548{
Soby Mathew981487a2015-07-13 14:10:57 +0100549 unsigned int parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
Soby Mathew011ca182015-07-29 17:05:03 +0100550 unsigned int level;
Achin Gupta0959db52013-12-02 17:33:04 +0000551
Soby Mathew981487a2015-07-13 14:10:57 +0100552 /* No locking required for level 0. Hence start locking from level 1 */
553 for (level = PSCI_CPU_PWR_LVL + 1; level <= end_pwrlvl; level++) {
554 psci_lock_get(&psci_non_cpu_pd_nodes[parent_idx]);
555 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
Achin Gupta0959db52013-12-02 17:33:04 +0000556 }
557}
558
559/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100560 * This function is passed a cpu_index and the highest level in the topology
561 * tree that the operation should be applied to. It releases the locks in order
562 * of decreasing power domain level in the range specified.
Achin Gupta0959db52013-12-02 17:33:04 +0000563 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100564void psci_release_pwr_domain_locks(unsigned int end_pwrlvl,
565 unsigned int cpu_idx)
Achin Gupta0959db52013-12-02 17:33:04 +0000566{
Soby Mathew981487a2015-07-13 14:10:57 +0100567 unsigned int parent_idx, parent_nodes[PLAT_MAX_PWR_LVL] = {0};
Achin Gupta0959db52013-12-02 17:33:04 +0000568 int level;
569
Soby Mathew981487a2015-07-13 14:10:57 +0100570 /* Get the parent nodes */
571 psci_get_parent_pwr_domain_nodes(cpu_idx, end_pwrlvl, parent_nodes);
Soby Mathew523d6332015-01-08 18:02:19 +0000572
Soby Mathew981487a2015-07-13 14:10:57 +0100573 /* Unlock top down. No unlocking required for level 0. */
574 for (level = end_pwrlvl; level >= PSCI_CPU_PWR_LVL + 1; level--) {
575 parent_idx = parent_nodes[level - 1];
576 psci_lock_release(&psci_non_cpu_pd_nodes[parent_idx]);
Achin Gupta0959db52013-12-02 17:33:04 +0000577 }
578}
579
580/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100581 * Simple routine to determine whether a mpidr is valid or not.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100582 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100583int psci_validate_mpidr(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100584{
Soby Mathew981487a2015-07-13 14:10:57 +0100585 if (plat_core_pos_by_mpidr(mpidr) < 0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100586 return PSCI_E_INVALID_PARAMS;
Soby Mathew981487a2015-07-13 14:10:57 +0100587
588 return PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100589}
590
591/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +0100592 * This function determines the full entrypoint information for the requested
Soby Mathew8595b872015-01-06 15:36:38 +0000593 * PSCI entrypoint on power on/resume and returns it.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100594 ******************************************************************************/
Soby Mathewf1f97a12015-07-15 12:13:26 +0100595static int psci_get_ns_ep_info(entry_point_info_t *ep,
Soby Mathew011ca182015-07-29 17:05:03 +0100596 uintptr_t entrypoint,
597 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100598{
Soby Mathew011ca182015-07-29 17:05:03 +0100599 unsigned long ep_attr, sctlr;
600 unsigned int daif, ee, mode;
601 unsigned long ns_scr_el3 = read_scr_el3();
602 unsigned long ns_sctlr_el1 = read_sctlr_el1();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100603
Andrew Thoelke4e126072014-06-04 21:10:52 +0100604 sctlr = ns_scr_el3 & SCR_HCE_BIT ? read_sctlr_el2() : ns_sctlr_el1;
605 ee = 0;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100606
Andrew Thoelke4e126072014-06-04 21:10:52 +0100607 ep_attr = NON_SECURE | EP_ST_DISABLE;
608 if (sctlr & SCTLR_EE_BIT) {
609 ep_attr |= EP_EE_BIG;
610 ee = 1;
611 }
Soby Mathew8595b872015-01-06 15:36:38 +0000612 SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100613
Soby Mathew8595b872015-01-06 15:36:38 +0000614 ep->pc = entrypoint;
615 memset(&ep->args, 0, sizeof(ep->args));
616 ep->args.arg0 = context_id;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100617
618 /*
619 * Figure out whether the cpu enters the non-secure address space
620 * in aarch32 or aarch64
621 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100622 if (ns_scr_el3 & SCR_RW_BIT) {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100623
624 /*
625 * Check whether a Thumb entry point has been provided for an
626 * aarch64 EL
627 */
628 if (entrypoint & 0x1)
Soby Mathewf1f97a12015-07-15 12:13:26 +0100629 return PSCI_E_INVALID_ADDRESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100630
Andrew Thoelke4e126072014-06-04 21:10:52 +0100631 mode = ns_scr_el3 & SCR_HCE_BIT ? MODE_EL2 : MODE_EL1;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100632
Soby Mathew8595b872015-01-06 15:36:38 +0000633 ep->spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100634 } else {
635
Andrew Thoelke4e126072014-06-04 21:10:52 +0100636 mode = ns_scr_el3 & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100637
638 /*
639 * TODO: Choose async. exception bits if HYP mode is not
640 * implemented according to the values of SCR.{AW, FW} bits
641 */
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100642 daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT;
643
Soby Mathew8595b872015-01-06 15:36:38 +0000644 ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, daif);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100645 }
646
Andrew Thoelke4e126072014-06-04 21:10:52 +0100647 return PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100648}
649
650/*******************************************************************************
Soby Mathewf1f97a12015-07-15 12:13:26 +0100651 * This function validates the entrypoint with the platform layer if the
652 * appropriate pm_ops hook is exported by the platform and returns the
653 * 'entry_point_info'.
654 ******************************************************************************/
655int psci_validate_entry_point(entry_point_info_t *ep,
Soby Mathew011ca182015-07-29 17:05:03 +0100656 uintptr_t entrypoint,
657 u_register_t context_id)
Soby Mathewf1f97a12015-07-15 12:13:26 +0100658{
659 int rc;
660
661 /* Validate the entrypoint using platform psci_ops */
662 if (psci_plat_pm_ops->validate_ns_entrypoint) {
663 rc = psci_plat_pm_ops->validate_ns_entrypoint(entrypoint);
664 if (rc != PSCI_E_SUCCESS)
665 return PSCI_E_INVALID_ADDRESS;
666 }
667
668 /*
669 * Verify and derive the re-entry information for
670 * the non-secure world from the non-secure state from
671 * where this call originated.
672 */
673 rc = psci_get_ns_ep_info(ep, entrypoint, context_id);
674 return rc;
675}
676
677/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100678 * Generic handler which is called when a cpu is physically powered on. It
Soby Mathew981487a2015-07-13 14:10:57 +0100679 * traverses the node information and finds the highest power level powered
680 * off and performs generic, architectural, platform setup and state management
681 * to power on that power level and power levels below it.
682 * e.g. For a cpu that's been powered on, it will call the platform specific
683 * code to enable the gic cpu interface and for a cluster it will enable
684 * coherency at the interconnect level in addition to gic cpu interface.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100685 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +0100686void psci_power_up_finish(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100687{
Soby Mathew011ca182015-07-29 17:05:03 +0100688 unsigned int end_pwrlvl, cpu_idx = plat_my_core_pos();
Soby Mathew981487a2015-07-13 14:10:57 +0100689 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
Achin Gupta4f6ad662013-10-25 09:08:21 +0100690
Achin Gupta4f6ad662013-10-25 09:08:21 +0100691 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100692 * Verify that we have been explicitly turned ON or resumed from
693 * suspend.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100694 */
Soby Mathew981487a2015-07-13 14:10:57 +0100695 if (psci_get_aff_info_state() == AFF_STATE_OFF) {
696 ERROR("Unexpected affinity info state");
James Morrissey40a6f642014-02-10 14:24:36 +0000697 panic();
Soby Mathew981487a2015-07-13 14:10:57 +0100698 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100699
700 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100701 * Get the maximum power domain level to traverse to after this cpu
702 * has been physically powered up.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100703 */
Soby Mathew981487a2015-07-13 14:10:57 +0100704 end_pwrlvl = get_power_on_target_pwrlvl();
Achin Guptaf6b9e992014-07-31 11:19:11 +0100705
706 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100707 * This function acquires the lock corresponding to each power level so
708 * that by the time all locks are taken, the system topology is snapshot
709 * and state management can be done safely.
Achin Guptaf6b9e992014-07-31 11:19:11 +0100710 */
Soby Mathew981487a2015-07-13 14:10:57 +0100711 psci_acquire_pwr_domain_locks(end_pwrlvl,
712 cpu_idx);
Achin Guptaf6b9e992014-07-31 11:19:11 +0100713
Soby Mathew981487a2015-07-13 14:10:57 +0100714 psci_get_target_local_pwr_states(end_pwrlvl, &state_info);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100715
716 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100717 * This CPU could be resuming from suspend or it could have just been
718 * turned on. To distinguish between these 2 cases, we examine the
719 * affinity state of the CPU:
720 * - If the affinity state is ON_PENDING then it has just been
721 * turned on.
722 * - Else it is resuming from suspend.
723 *
724 * Depending on the type of warm reset identified, choose the right set
725 * of power management handler and perform the generic, architecture
726 * and platform specific handling.
Achin Guptacab78e42014-07-28 00:09:01 +0100727 */
Soby Mathew981487a2015-07-13 14:10:57 +0100728 if (psci_get_aff_info_state() == AFF_STATE_ON_PENDING)
729 psci_cpu_on_finish(cpu_idx, &state_info);
730 else
731 psci_cpu_suspend_finish(cpu_idx, &state_info);
Achin Guptacab78e42014-07-28 00:09:01 +0100732
733 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100734 * Set the requested and target state of this CPU and all the higher
735 * power domains which are ancestors of this CPU to run.
Achin Guptaf6b9e992014-07-31 11:19:11 +0100736 */
Soby Mathew981487a2015-07-13 14:10:57 +0100737 psci_set_pwr_domains_to_run(end_pwrlvl);
Achin Guptaf6b9e992014-07-31 11:19:11 +0100738
739 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100740 * This loop releases the lock corresponding to each power level
Achin Gupta0959db52013-12-02 17:33:04 +0000741 * in the reverse order to which they were acquired.
742 */
Soby Mathew981487a2015-07-13 14:10:57 +0100743 psci_release_pwr_domain_locks(end_pwrlvl,
744 cpu_idx);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100745}
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000746
747/*******************************************************************************
748 * This function initializes the set of hooks that PSCI invokes as part of power
749 * management operation. The power management hooks are expected to be provided
750 * by the SPD, after it finishes all its initialization
751 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100752void psci_register_spd_pm_hook(const spd_pm_ops_t *pm)
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000753{
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000754 assert(pm);
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000755 psci_spd_pm = pm;
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000756
757 if (pm->svc_migrate)
758 psci_caps |= define_psci_cap(PSCI_MIG_AARCH64);
759
760 if (pm->svc_migrate_info)
761 psci_caps |= define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64)
762 | define_psci_cap(PSCI_MIG_INFO_TYPE);
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000763}
Juan Castillo4dc4a472014-08-12 11:17:06 +0100764
765/*******************************************************************************
Soby Mathew110fe362014-10-23 10:35:34 +0100766 * This function invokes the migrate info hook in the spd_pm_ops. It performs
767 * the necessary return value validation. If the Secure Payload is UP and
768 * migrate capable, it returns the mpidr of the CPU on which the Secure payload
769 * is resident through the mpidr parameter. Else the value of the parameter on
770 * return is undefined.
771 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100772int psci_spd_migrate_info(u_register_t *mpidr)
Soby Mathew110fe362014-10-23 10:35:34 +0100773{
774 int rc;
775
776 if (!psci_spd_pm || !psci_spd_pm->svc_migrate_info)
777 return PSCI_E_NOT_SUPPORTED;
778
779 rc = psci_spd_pm->svc_migrate_info(mpidr);
780
781 assert(rc == PSCI_TOS_UP_MIG_CAP || rc == PSCI_TOS_NOT_UP_MIG_CAP \
782 || rc == PSCI_TOS_NOT_PRESENT_MP || rc == PSCI_E_NOT_SUPPORTED);
783
784 return rc;
785}
786
787
788/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100789 * This function prints the state of all power domains present in the
Juan Castillo4dc4a472014-08-12 11:17:06 +0100790 * system
791 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +0100792void psci_print_power_domain_map(void)
Juan Castillo4dc4a472014-08-12 11:17:06 +0100793{
794#if LOG_LEVEL >= LOG_LEVEL_INFO
Juan Castillo4dc4a472014-08-12 11:17:06 +0100795 unsigned int idx;
Soby Mathew981487a2015-07-13 14:10:57 +0100796 plat_local_state_t state;
797 plat_local_state_type_t state_type;
798
Juan Castillo4dc4a472014-08-12 11:17:06 +0100799 /* This array maps to the PSCI_STATE_X definitions in psci.h */
Soby Mathew981487a2015-07-13 14:10:57 +0100800 static const char *psci_state_type_str[] = {
Juan Castillo4dc4a472014-08-12 11:17:06 +0100801 "ON",
Soby Mathew981487a2015-07-13 14:10:57 +0100802 "RETENTION",
Juan Castillo4dc4a472014-08-12 11:17:06 +0100803 "OFF",
Juan Castillo4dc4a472014-08-12 11:17:06 +0100804 };
805
Soby Mathew981487a2015-07-13 14:10:57 +0100806 INFO("PSCI Power Domain Map:\n");
807 for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - PLATFORM_CORE_COUNT);
808 idx++) {
809 state_type = find_local_state_type(
810 psci_non_cpu_pd_nodes[idx].local_state);
811 INFO(" Domain Node : Level %u, parent_node %d,"
812 " State %s (0x%x)\n",
813 psci_non_cpu_pd_nodes[idx].level,
814 psci_non_cpu_pd_nodes[idx].parent_node,
815 psci_state_type_str[state_type],
816 psci_non_cpu_pd_nodes[idx].local_state);
817 }
818
819 for (idx = 0; idx < PLATFORM_CORE_COUNT; idx++) {
820 state = psci_get_cpu_local_state_by_idx(idx);
821 state_type = find_local_state_type(state);
822 INFO(" CPU Node : MPID 0x%lx, parent_node %d,"
823 " State %s (0x%x)\n",
824 psci_cpu_pd_nodes[idx].mpidr,
825 psci_cpu_pd_nodes[idx].parent_node,
826 psci_state_type_str[state_type],
827 psci_get_cpu_local_state_by_idx(idx));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100828 }
829#endif
830}
Soby Mathew981487a2015-07-13 14:10:57 +0100831
832#if ENABLE_PLAT_COMPAT
833/*******************************************************************************
834 * PSCI Compatibility helper function to return the 'power_state' parameter of
835 * the PSCI CPU SUSPEND request for the current CPU. Returns PSCI_INVALID_DATA
836 * if not invoked within CPU_SUSPEND for the current CPU.
837 ******************************************************************************/
838int psci_get_suspend_powerstate(void)
839{
840 /* Sanity check to verify that CPU is within CPU_SUSPEND */
841 if (psci_get_aff_info_state() == AFF_STATE_ON &&
842 !is_local_state_run(psci_get_cpu_local_state()))
843 return psci_power_state_compat[plat_my_core_pos()];
844
845 return PSCI_INVALID_DATA;
846}
847
848/*******************************************************************************
849 * PSCI Compatibility helper function to return the state id of the current
850 * cpu encoded in the 'power_state' parameter. Returns PSCI_INVALID_DATA
851 * if not invoked within CPU_SUSPEND for the current CPU.
852 ******************************************************************************/
853int psci_get_suspend_stateid(void)
854{
855 unsigned int power_state;
856 power_state = psci_get_suspend_powerstate();
857 if (power_state != PSCI_INVALID_DATA)
858 return psci_get_pstate_id(power_state);
859
860 return PSCI_INVALID_DATA;
861}
862
863/*******************************************************************************
864 * PSCI Compatibility helper function to return the state id encoded in the
865 * 'power_state' parameter of the CPU specified by 'mpidr'. Returns
866 * PSCI_INVALID_DATA if the CPU is not in CPU_SUSPEND.
867 ******************************************************************************/
868int psci_get_suspend_stateid_by_mpidr(unsigned long mpidr)
869{
870 int cpu_idx = plat_core_pos_by_mpidr(mpidr);
871
872 if (cpu_idx == -1)
873 return PSCI_INVALID_DATA;
874
875 /* Sanity check to verify that the CPU is in CPU_SUSPEND */
876 if (psci_get_aff_info_state_by_idx(cpu_idx) == AFF_STATE_ON &&
877 !is_local_state_run(psci_get_cpu_local_state_by_idx(cpu_idx)))
878 return psci_get_pstate_id(psci_power_state_compat[cpu_idx]);
879
880 return PSCI_INVALID_DATA;
881}
882
883/*******************************************************************************
884 * This function returns highest affinity level which is in OFF
885 * state. The affinity instance with which the level is associated is
886 * determined by the caller.
887 ******************************************************************************/
888unsigned int psci_get_max_phys_off_afflvl(void)
889{
890 psci_power_state_t state_info;
891
892 memset(&state_info, 0, sizeof(state_info));
893 psci_get_target_local_pwr_states(PLAT_MAX_PWR_LVL, &state_info);
894
895 return psci_find_target_suspend_lvl(&state_info);
896}
897
898/*******************************************************************************
899 * PSCI Compatibility helper function to return target affinity level requested
900 * for the CPU_SUSPEND. This function assumes affinity levels correspond to
901 * power domain levels on the platform.
902 ******************************************************************************/
903int psci_get_suspend_afflvl(void)
904{
905 return psci_get_suspend_pwrlvl();
906}
907
908#endif