| Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <arch_helpers.h> |
| 33 | #include <assert.h> |
| 34 | #include <denver.h> |
| 35 | #include <debug.h> |
| 36 | #include <flowctrl.h> |
| 37 | #include <mmio.h> |
| 38 | #include <platform_def.h> |
| 39 | #include <pmc.h> |
| 40 | #include <psci.h> |
| 41 | #include <tegra_def.h> |
| 42 | #include <tegra_private.h> |
| 43 | |
| 44 | /* |
| 45 | * Register used to clear CPU reset signals. Each CPU has two reset |
| 46 | * signals: CPU reset (3:0) and Core reset (19:16) |
| 47 | */ |
| 48 | #define CPU_CMPLX_RESET_CLR 0x344 |
| 49 | #define CPU_CORE_RESET_MASK 0x10001 |
| 50 | |
| 51 | static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; |
| 52 | |
| 53 | int32_t tegra_soc_validate_power_state(unsigned int power_state) |
| 54 | { |
| 55 | /* Sanity check the requested afflvl */ |
| 56 | if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) { |
| 57 | /* |
| 58 | * It's possible to enter standby only on affinity level 0 i.e. |
| 59 | * a cpu on Tegra. Ignore any other affinity level. |
| 60 | */ |
| 61 | if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0) |
| 62 | return PSCI_E_INVALID_PARAMS; |
| 63 | } |
| 64 | |
| 65 | /* Sanity check the requested state id */ |
| 66 | if (psci_get_pstate_id(power_state) != PLAT_SYS_SUSPEND_STATE_ID) { |
| 67 | ERROR("unsupported state id\n"); |
| 68 | return PSCI_E_NOT_SUPPORTED; |
| 69 | } |
| 70 | |
| 71 | return PSCI_E_SUCCESS; |
| 72 | } |
| 73 | |
| 74 | int tegra_soc_prepare_cpu_on(unsigned long mpidr) |
| 75 | { |
| 76 | int cpu = mpidr & MPIDR_CPU_MASK; |
| 77 | uint32_t mask = CPU_CORE_RESET_MASK << cpu; |
| 78 | |
| 79 | if (cpu_powergate_mask[cpu] == 0) { |
| 80 | |
| 81 | /* Deassert CPU reset signals */ |
| 82 | mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); |
| 83 | |
| 84 | /* Power on CPU using PMC */ |
| 85 | tegra_pmc_cpu_on(cpu); |
| 86 | |
| 87 | /* Fill in the CPU powergate mask */ |
| 88 | cpu_powergate_mask[cpu] = 1; |
| 89 | |
| 90 | } else { |
| 91 | /* Power on CPU using Flow Controller */ |
| 92 | tegra_fc_cpu_on(cpu); |
| 93 | } |
| 94 | |
| 95 | return PSCI_E_SUCCESS; |
| 96 | } |
| 97 | |
| 98 | int tegra_soc_prepare_cpu_off(unsigned long mpidr) |
| 99 | { |
| 100 | tegra_fc_cpu_off(mpidr & MPIDR_CPU_MASK); |
| 101 | return PSCI_E_SUCCESS; |
| 102 | } |
| 103 | |
| 104 | int tegra_soc_prepare_cpu_suspend(unsigned int id, unsigned int afflvl) |
| 105 | { |
| 106 | /* Nothing to be done for lower affinity levels */ |
| 107 | if (afflvl < MPIDR_AFFLVL2) |
| 108 | return PSCI_E_SUCCESS; |
| 109 | |
| 110 | /* Enter system suspend state */ |
| 111 | tegra_pm_system_suspend_entry(); |
| 112 | |
| 113 | /* Allow restarting CPU #1 using PMC on suspend exit */ |
| 114 | cpu_powergate_mask[1] = 0; |
| 115 | |
| 116 | /* Program FC to enter suspend state */ |
| 117 | tegra_fc_cpu_idle(read_mpidr()); |
| 118 | |
| 119 | /* Suspend DCO operations */ |
| 120 | write_actlr_el1(id); |
| 121 | |
| 122 | return PSCI_E_SUCCESS; |
| 123 | } |