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git01.mediatek.com / filogic / atf / 483e5ac469d556e47dd02adb79909bd8f1374298 / . / include / export / common / tbbr / tbbr_img_def_exp.h
blob: 98a00999d55c88f5ec7f16db949a8207c3126dda [file] [log] [blame]
Julius Werner2a231e32019-05-28 21:03:58 -0700[diff] [blame]1/*
laurenw-arm483e5ac2022-04-21 15:49:00 -0500[diff] [blame^]2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
Julius Werner2a231e32019-05-28 21:03:58 -0700[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_TBBR_TBBR_IMG_DEF_EXP_H
8#define ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_TBBR_TBBR_IMG_DEF_EXP_H
9
10/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
11
12#include "../../lib/utils_def_exp.h"
13
14/* Firmware Image Package */
15#define FIP_IMAGE_ID U(0)
16
17/* Trusted Boot Firmware BL2 */
18#define BL2_IMAGE_ID U(1)
19
20/* SCP Firmware SCP_BL2 */
21#define SCP_BL2_IMAGE_ID U(2)
22
23/* EL3 Runtime Firmware BL31 */
24#define BL31_IMAGE_ID U(3)
25
26/* Secure Payload BL32 (Trusted OS) */
27#define BL32_IMAGE_ID U(4)
28
29/* Non-Trusted Firmware BL33 */
30#define BL33_IMAGE_ID U(5)
31
32/* Certificates */
33#define TRUSTED_BOOT_FW_CERT_ID U(6)
34#define TRUSTED_KEY_CERT_ID U(7)
35
36#define SCP_FW_KEY_CERT_ID U(8)
37#define SOC_FW_KEY_CERT_ID U(9)
38#define TRUSTED_OS_FW_KEY_CERT_ID U(10)
39#define NON_TRUSTED_FW_KEY_CERT_ID U(11)
40
41#define SCP_FW_CONTENT_CERT_ID U(12)
42#define SOC_FW_CONTENT_CERT_ID U(13)
43#define TRUSTED_OS_FW_CONTENT_CERT_ID U(14)
44#define NON_TRUSTED_FW_CONTENT_CERT_ID U(15)
45
46/* Non-Trusted ROM Firmware NS_BL1U */
47#define NS_BL1U_IMAGE_ID U(16)
48
49/* Trusted FWU Certificate */
50#define FWU_CERT_ID U(17)
51
52/* Trusted FWU SCP Firmware SCP_BL2U */
53#define SCP_BL2U_IMAGE_ID U(18)
54
55/* Trusted FWU Boot Firmware BL2U */
56#define BL2U_IMAGE_ID U(19)
57
58/* Non-Trusted FWU Firmware NS_BL2U */
59#define NS_BL2U_IMAGE_ID U(20)
60
61/* Secure Payload BL32_EXTRA1 (Trusted OS Extra1) */
62#define BL32_EXTRA1_IMAGE_ID U(21)
63
64/* Secure Payload BL32_EXTRA2 (Trusted OS Extra2) */
65#define BL32_EXTRA2_IMAGE_ID U(22)
66
67/* HW_CONFIG (e.g. Kernel DT) */
68#define HW_CONFIG_ID U(23)
69
70/* TB_FW_CONFIG */
71#define TB_FW_CONFIG_ID U(24)
72
73/* SOC_FW_CONFIG */
74#define SOC_FW_CONFIG_ID U(25)
75
76/* TOS_FW_CONFIG */
77#define TOS_FW_CONFIG_ID U(26)
78
79/* NT_FW_CONFIG */
80#define NT_FW_CONFIG_ID U(27)
81
82/* GPT Partition */
83#define GPT_IMAGE_ID U(28)
84
85/* Binary with STM32 header */
86#define STM32_IMAGE_ID U(29)
87
Sumit Garg617e2152019-11-15 15:34:55 +0530[diff] [blame]88/* Encrypted image identifier */
89#define ENC_IMAGE_ID U(30)
90
Louis Mayencourt244027d2020-06-11 21:15:15 +0100[diff] [blame]91/* FW_CONFIG */
92#define FW_CONFIG_ID U(31)
93
Manish V Badarkhe7ef036f2021-06-20 20:35:25 +0100[diff] [blame]94/*
95 * Primary FWU metadata image ID
96 */
97#define FWU_METADATA_IMAGE_ID U(32)
98
99/*
100 * Backup FWU metadata image ID
101 */
102#define BKUP_FWU_METADATA_IMAGE_ID U(33)
103
Zelalem Aweke4d37db82021-07-11 18:33:20 -0500[diff] [blame]104/* Realm Monitor Manager (RMM) */
105#define RMM_IMAGE_ID U(34)
106
laurenw-arm483e5ac2022-04-21 15:49:00 -0500[diff] [blame^]107/* CCA Content Certificate ID */
108#define CCA_CONTENT_CERT_ID U(35)
109
110/* Core SWD Key Certificate ID */
111#define CORE_SWD_KEY_CERT_ID U(36)
112
113/* Platform Key Certificate ID */
114#define PLAT_KEY_CERT_ID U(37)
115
Manish Pandey5f8e1a02020-05-27 22:40:10 +0100[diff] [blame]116/* Max Images */
laurenw-arm483e5ac2022-04-21 15:49:00 -0500[diff] [blame^]117#define MAX_IMAGE_IDS U(38)
Julius Werner2a231e32019-05-28 21:03:58 -0700[diff] [blame]118
119#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_TBBR_TBBR_IMG_DEF_EXP_H */