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Soby Mathewc6820d12016-05-09 17:49:55 +01001/*
Dimitris Papastamos0a4cded2018-01-02 11:37:02 +00002 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Soby Mathewc6820d12016-05-09 17:49:55 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewc6820d12016-05-09 17:49:55 +01005 */
6
7#ifndef __ARCH_H__
8#define __ARCH_H__
9
Isla Mitchell02c63072017-07-21 14:44:36 +010010#include <utils_def.h>
11
Soby Mathewc6820d12016-05-09 17:49:55 +010012/*******************************************************************************
13 * MIDR bit definitions
14 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010015#define MIDR_IMPL_MASK U(0xff)
16#define MIDR_IMPL_SHIFT U(24)
17#define MIDR_VAR_SHIFT U(20)
18#define MIDR_VAR_BITS U(4)
19#define MIDR_REV_SHIFT U(0)
20#define MIDR_REV_BITS U(4)
21#define MIDR_PN_MASK U(0xfff)
22#define MIDR_PN_SHIFT U(4)
Soby Mathewc6820d12016-05-09 17:49:55 +010023
24/*******************************************************************************
25 * MPIDR macros
26 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010027#define MPIDR_MT_MASK (U(1) << 24)
Soby Mathewc6820d12016-05-09 17:49:55 +010028#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
29#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010030#define MPIDR_AFFINITY_BITS U(8)
31#define MPIDR_AFFLVL_MASK U(0xff)
32#define MPIDR_AFFLVL_SHIFT U(3)
33#define MPIDR_AFF0_SHIFT U(0)
34#define MPIDR_AFF1_SHIFT U(8)
35#define MPIDR_AFF2_SHIFT U(16)
36#define MPIDR_AFFINITY_MASK U(0x00ffffff)
37#define MPIDR_AFFLVL0 U(0)
38#define MPIDR_AFFLVL1 U(1)
39#define MPIDR_AFFLVL2 U(2)
Soby Mathewc6820d12016-05-09 17:49:55 +010040
41#define MPIDR_AFFLVL0_VAL(mpidr) \
42 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
43#define MPIDR_AFFLVL1_VAL(mpidr) \
44 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
45#define MPIDR_AFFLVL2_VAL(mpidr) \
46 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010047#define MPIDR_AFFLVL3_VAL(mpidr) U(0)
Soby Mathewc6820d12016-05-09 17:49:55 +010048
49/*
50 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
51 * add one while using this macro to define array sizes.
52 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010053#define MPIDR_MAX_AFFLVL U(2)
Soby Mathewc6820d12016-05-09 17:49:55 +010054
55/* Data Cache set/way op type defines */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010056#define DC_OP_ISW U(0x0)
57#define DC_OP_CISW U(0x1)
58#define DC_OP_CSW U(0x2)
Soby Mathewc6820d12016-05-09 17:49:55 +010059
60/*******************************************************************************
61 * Generic timer memory mapped registers & offsets
62 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010063#define CNTCR_OFF U(0x000)
64#define CNTFID_OFF U(0x020)
Soby Mathewc6820d12016-05-09 17:49:55 +010065
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010066#define CNTCR_EN (U(1) << 0)
67#define CNTCR_HDBG (U(1) << 1)
Soby Mathewc6820d12016-05-09 17:49:55 +010068#define CNTCR_FCREQ(x) ((x) << 8)
69
70/*******************************************************************************
71 * System register bit definitions
72 ******************************************************************************/
73/* CLIDR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010074#define LOUIS_SHIFT U(21)
75#define LOC_SHIFT U(24)
76#define CLIDR_FIELD_WIDTH U(3)
Soby Mathewc6820d12016-05-09 17:49:55 +010077
78/* CSSELR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010079#define LEVEL_SHIFT U(1)
Soby Mathewc6820d12016-05-09 17:49:55 +010080
Dimitris Papastamosdda48b02017-10-17 14:03:14 +010081/* ID_PFR0 definitions */
82#define ID_PFR0_AMU_SHIFT U(20)
83#define ID_PFR0_AMU_LENGTH U(4)
84#define ID_PFR0_AMU_MASK U(0xf)
85
Soby Mathewc6820d12016-05-09 17:49:55 +010086/* ID_PFR1 definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010087#define ID_PFR1_VIRTEXT_SHIFT U(12)
88#define ID_PFR1_VIRTEXT_MASK U(0xf)
Soby Mathewc6820d12016-05-09 17:49:55 +010089#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
90 & ID_PFR1_VIRTEXT_MASK)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010091#define ID_PFR1_GIC_SHIFT U(28)
92#define ID_PFR1_GIC_MASK U(0xf)
Soby Mathewc6820d12016-05-09 17:49:55 +010093
94/* SCTLR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010095#define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \
96 (U(1) << 3))
Etienne Carriere70a004b2017-11-05 22:56:03 +010097#if ARM_ARCH_MAJOR == 7
98#define SCTLR_RES1 SCTLR_RES1_DEF
99#else
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100100#define SCTLR_RES1 (SCTLR_RES1_DEF | (U(1) << 11))
Etienne Carriere70a004b2017-11-05 22:56:03 +0100101#endif
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100102#define SCTLR_M_BIT (U(1) << 0)
103#define SCTLR_A_BIT (U(1) << 1)
104#define SCTLR_C_BIT (U(1) << 2)
105#define SCTLR_CP15BEN_BIT (U(1) << 5)
106#define SCTLR_ITD_BIT (U(1) << 7)
107#define SCTLR_Z_BIT (U(1) << 11)
108#define SCTLR_I_BIT (U(1) << 12)
109#define SCTLR_V_BIT (U(1) << 13)
110#define SCTLR_RR_BIT (U(1) << 14)
111#define SCTLR_NTWI_BIT (U(1) << 16)
112#define SCTLR_NTWE_BIT (U(1) << 18)
113#define SCTLR_WXN_BIT (U(1) << 19)
114#define SCTLR_UWXN_BIT (U(1) << 20)
115#define SCTLR_EE_BIT (U(1) << 25)
116#define SCTLR_TRE_BIT (U(1) << 28)
117#define SCTLR_AFE_BIT (U(1) << 29)
118#define SCTLR_TE_BIT (U(1) << 30)
David Cunadofee86532017-04-13 22:38:29 +0100119#define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \
120 SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT)
Soby Mathewc6820d12016-05-09 17:49:55 +0100121
dp-arm595d0d52017-02-08 11:51:50 +0000122/* SDCR definitions */
123#define SDCR_SPD(x) ((x) << 14)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100124#define SDCR_SPD_LEGACY U(0x0)
125#define SDCR_SPD_DISABLE U(0x2)
126#define SDCR_SPD_ENABLE U(0x3)
127#define SDCR_RESET_VAL U(0x0)
dp-arm595d0d52017-02-08 11:51:50 +0000128
Soby Mathewc6820d12016-05-09 17:49:55 +0100129/* HSCTLR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100130#define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
131 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
132 (U(1) << 11) | (U(1) << 4) | (U(1) << 3))
133
134#define HSCTLR_M_BIT (U(1) << 0)
135#define HSCTLR_A_BIT (U(1) << 1)
136#define HSCTLR_C_BIT (U(1) << 2)
137#define HSCTLR_CP15BEN_BIT (U(1) << 5)
138#define HSCTLR_ITD_BIT (U(1) << 7)
139#define HSCTLR_SED_BIT (U(1) << 8)
140#define HSCTLR_I_BIT (U(1) << 12)
141#define HSCTLR_WXN_BIT (U(1) << 19)
142#define HSCTLR_EE_BIT (U(1) << 25)
143#define HSCTLR_TE_BIT (U(1) << 30)
Soby Mathewc6820d12016-05-09 17:49:55 +0100144
145/* CPACR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100146#define CPACR_FPEN(x) ((x) << 20)
147#define CPACR_FP_TRAP_PL0 U(0x1)
148#define CPACR_FP_TRAP_ALL U(0x2)
149#define CPACR_FP_TRAP_NONE U(0x3)
Soby Mathewc6820d12016-05-09 17:49:55 +0100150
151/* SCR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100152#define SCR_TWE_BIT (U(1) << 13)
153#define SCR_TWI_BIT (U(1) << 12)
154#define SCR_SIF_BIT (U(1) << 9)
155#define SCR_HCE_BIT (U(1) << 8)
156#define SCR_SCD_BIT (U(1) << 7)
157#define SCR_NET_BIT (U(1) << 6)
158#define SCR_AW_BIT (U(1) << 5)
159#define SCR_FW_BIT (U(1) << 4)
160#define SCR_EA_BIT (U(1) << 3)
161#define SCR_FIQ_BIT (U(1) << 2)
162#define SCR_IRQ_BIT (U(1) << 1)
163#define SCR_NS_BIT (U(1) << 0)
164#define SCR_VALID_BIT_MASK U(0x33ff)
165#define SCR_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100166
167#define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT)
168
169/* HCR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100170#define HCR_AMO_BIT (U(1) << 5)
171#define HCR_IMO_BIT (U(1) << 4)
172#define HCR_FMO_BIT (U(1) << 3)
173#define HCR_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100174
175/* CNTHCTL definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100176#define CNTHCTL_RESET_VAL U(0x0)
177#define PL1PCEN_BIT (U(1) << 1)
178#define PL1PCTEN_BIT (U(1) << 0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100179
180/* CNTKCTL definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100181#define PL0PTEN_BIT (U(1) << 9)
182#define PL0VTEN_BIT (U(1) << 8)
183#define PL0PCTEN_BIT (U(1) << 0)
184#define PL0VCTEN_BIT (U(1) << 1)
185#define EVNTEN_BIT (U(1) << 2)
186#define EVNTDIR_BIT (U(1) << 3)
187#define EVNTI_SHIFT U(4)
188#define EVNTI_MASK U(0xf)
Soby Mathewc6820d12016-05-09 17:49:55 +0100189
190/* HCPTR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100191#define HCPTR_RES1 ((U(1) << 13) | (U(1) << 12) | U(0x3ff))
192#define TCPAC_BIT (U(1) << 31)
193#define TAM_BIT (U(1) << 30)
194#define TTA_BIT (U(1) << 20)
Sandrine Bailleux6061c452018-07-13 10:04:12 +0200195#define TCP11_BIT (U(1) << 11)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100196#define TCP10_BIT (U(1) << 10)
David Cunadofee86532017-04-13 22:38:29 +0100197#define HCPTR_RESET_VAL HCPTR_RES1
198
199/* VTTBR defintions */
200#define VTTBR_RESET_VAL ULL(0x0)
201#define VTTBR_VMID_MASK ULL(0xff)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100202#define VTTBR_VMID_SHIFT U(48)
203#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
204#define VTTBR_BADDR_SHIFT U(0)
David Cunadofee86532017-04-13 22:38:29 +0100205
206/* HDCR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100207#define HDCR_RESET_VAL U(0x0)
David Cunadofee86532017-04-13 22:38:29 +0100208
209/* HSTR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100210#define HSTR_RESET_VAL U(0x0)
David Cunadofee86532017-04-13 22:38:29 +0100211
212/* CNTHP_CTL definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100213#define CNTHP_CTL_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100214
215/* NASCR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100216#define NSASEDIS_BIT (U(1) << 15)
217#define NSTRCDIS_BIT (U(1) << 20)
David Cunadofee86532017-04-13 22:38:29 +0100218/* NOTE: correct typo in the definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100219#define NSACR_CP11_BIT (U(1) << 11)
220#define NSACR_CP10_BIT (U(1) << 10)
221#define NSACR_IMP_DEF_MASK (U(0x7) << 16)
David Cunadofee86532017-04-13 22:38:29 +0100222#define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100223#define NSACR_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100224
225/* CPACR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100226#define ASEDIS_BIT (U(1) << 31)
227#define TRCDIS_BIT (U(1) << 28)
228#define CPACR_CP11_SHIFT U(22)
229#define CPACR_CP10_SHIFT U(20)
230#define CPACR_ENABLE_FP_ACCESS ((U(0x3) << CPACR_CP11_SHIFT) |\
231 (U(0x3) << CPACR_CP10_SHIFT))
232#define CPACR_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100233
234/* FPEXC definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100235#define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8))
236#define FPEXC_EN_BIT (U(1) << 30)
David Cunadofee86532017-04-13 22:38:29 +0100237#define FPEXC_RESET_VAL FPEXC_RES1
Soby Mathewc6820d12016-05-09 17:49:55 +0100238
239/* SPSR/CPSR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100240#define SPSR_FIQ_BIT (U(1) << 0)
241#define SPSR_IRQ_BIT (U(1) << 1)
242#define SPSR_ABT_BIT (U(1) << 2)
243#define SPSR_AIF_SHIFT U(6)
244#define SPSR_AIF_MASK U(0x7)
Soby Mathewc6820d12016-05-09 17:49:55 +0100245
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100246#define SPSR_E_SHIFT U(9)
247#define SPSR_E_MASK U(0x1)
248#define SPSR_E_LITTLE U(0)
249#define SPSR_E_BIG U(1)
Soby Mathewc6820d12016-05-09 17:49:55 +0100250
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100251#define SPSR_T_SHIFT U(5)
252#define SPSR_T_MASK U(0x1)
253#define SPSR_T_ARM U(0)
254#define SPSR_T_THUMB U(1)
Soby Mathewc6820d12016-05-09 17:49:55 +0100255
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100256#define SPSR_MODE_SHIFT U(0)
257#define SPSR_MODE_MASK U(0x7)
Soby Mathewc6820d12016-05-09 17:49:55 +0100258
259#define DISABLE_ALL_EXCEPTIONS \
260 (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT)
261
262/*
263 * TTBCR definitions
264 */
265/* The ARM Trusted Firmware uses the long descriptor format */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100266#define TTBCR_EAE_BIT (U(1) << 31)
Soby Mathewc6820d12016-05-09 17:49:55 +0100267
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100268#define TTBCR_SH1_NON_SHAREABLE (U(0x0) << 28)
269#define TTBCR_SH1_OUTER_SHAREABLE (U(0x2) << 28)
270#define TTBCR_SH1_INNER_SHAREABLE (U(0x3) << 28)
Soby Mathewc6820d12016-05-09 17:49:55 +0100271
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100272#define TTBCR_RGN1_OUTER_NC (U(0x0) << 26)
273#define TTBCR_RGN1_OUTER_WBA (U(0x1) << 26)
274#define TTBCR_RGN1_OUTER_WT (U(0x2) << 26)
275#define TTBCR_RGN1_OUTER_WBNA (U(0x3) << 26)
Soby Mathewc6820d12016-05-09 17:49:55 +0100276
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100277#define TTBCR_RGN1_INNER_NC (U(0x0) << 24)
278#define TTBCR_RGN1_INNER_WBA (U(0x1) << 24)
279#define TTBCR_RGN1_INNER_WT (U(0x2) << 24)
280#define TTBCR_RGN1_INNER_WBNA (U(0x3) << 24)
Soby Mathewc6820d12016-05-09 17:49:55 +0100281
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100282#define TTBCR_EPD1_BIT (U(1) << 23)
283#define TTBCR_A1_BIT (U(1) << 22)
Soby Mathewc6820d12016-05-09 17:49:55 +0100284
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100285#define TTBCR_T1SZ_SHIFT U(16)
286#define TTBCR_T1SZ_MASK U(0x7)
287#define TTBCR_TxSZ_MIN U(0)
288#define TTBCR_TxSZ_MAX U(7)
Soby Mathewc6820d12016-05-09 17:49:55 +0100289
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100290#define TTBCR_SH0_NON_SHAREABLE (U(0x0) << 12)
291#define TTBCR_SH0_OUTER_SHAREABLE (U(0x2) << 12)
292#define TTBCR_SH0_INNER_SHAREABLE (U(0x3) << 12)
Soby Mathewc6820d12016-05-09 17:49:55 +0100293
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100294#define TTBCR_RGN0_OUTER_NC (U(0x0) << 10)
295#define TTBCR_RGN0_OUTER_WBA (U(0x1) << 10)
296#define TTBCR_RGN0_OUTER_WT (U(0x2) << 10)
297#define TTBCR_RGN0_OUTER_WBNA (U(0x3) << 10)
Soby Mathewc6820d12016-05-09 17:49:55 +0100298
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100299#define TTBCR_RGN0_INNER_NC (U(0x0) << 8)
300#define TTBCR_RGN0_INNER_WBA (U(0x1) << 8)
301#define TTBCR_RGN0_INNER_WT (U(0x2) << 8)
302#define TTBCR_RGN0_INNER_WBNA (U(0x3) << 8)
Soby Mathewc6820d12016-05-09 17:49:55 +0100303
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100304#define TTBCR_EPD0_BIT (U(1) << 7)
305#define TTBCR_T0SZ_SHIFT U(0)
306#define TTBCR_T0SZ_MASK U(0x7)
Soby Mathewc6820d12016-05-09 17:49:55 +0100307
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100308/*
309 * HTCR definitions
310 */
311#define HTCR_RES1 ((U(1) << 31) | (U(1) << 23))
312
313#define HTCR_SH0_NON_SHAREABLE (U(0x0) << 12)
314#define HTCR_SH0_OUTER_SHAREABLE (U(0x2) << 12)
315#define HTCR_SH0_INNER_SHAREABLE (U(0x3) << 12)
316
317#define HTCR_RGN0_OUTER_NC (U(0x0) << 10)
318#define HTCR_RGN0_OUTER_WBA (U(0x1) << 10)
319#define HTCR_RGN0_OUTER_WT (U(0x2) << 10)
320#define HTCR_RGN0_OUTER_WBNA (U(0x3) << 10)
321
322#define HTCR_RGN0_INNER_NC (U(0x0) << 8)
323#define HTCR_RGN0_INNER_WBA (U(0x1) << 8)
324#define HTCR_RGN0_INNER_WT (U(0x2) << 8)
325#define HTCR_RGN0_INNER_WBNA (U(0x3) << 8)
326
327#define HTCR_T0SZ_SHIFT U(0)
328#define HTCR_T0SZ_MASK U(0x7)
329
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100330#define MODE_RW_SHIFT U(0x4)
331#define MODE_RW_MASK U(0x1)
332#define MODE_RW_32 U(0x1)
Soby Mathewc6820d12016-05-09 17:49:55 +0100333
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100334#define MODE32_SHIFT U(0)
335#define MODE32_MASK U(0x1f)
336#define MODE32_usr U(0x10)
337#define MODE32_fiq U(0x11)
338#define MODE32_irq U(0x12)
339#define MODE32_svc U(0x13)
340#define MODE32_mon U(0x16)
341#define MODE32_abt U(0x17)
342#define MODE32_hyp U(0x1a)
343#define MODE32_und U(0x1b)
344#define MODE32_sys U(0x1f)
Soby Mathewc6820d12016-05-09 17:49:55 +0100345
346#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
347
348#define SPSR_MODE32(mode, isa, endian, aif) \
349 (MODE_RW_32 << MODE_RW_SHIFT | \
350 ((mode) & MODE32_MASK) << MODE32_SHIFT | \
351 ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \
352 ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \
353 ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
354
355/*
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100356 * TTBR definitions
357 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100358#define TTBR_CNP_BIT ULL(0x1)
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100359
360/*
Soby Mathewc6820d12016-05-09 17:49:55 +0100361 * CTR definitions
362 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100363#define CTR_CWG_SHIFT U(24)
364#define CTR_CWG_MASK U(0xf)
365#define CTR_ERG_SHIFT U(20)
366#define CTR_ERG_MASK U(0xf)
367#define CTR_DMINLINE_SHIFT U(16)
368#define CTR_DMINLINE_WIDTH U(4)
369#define CTR_DMINLINE_MASK ((U(1) << 4) - U(1))
370#define CTR_L1IP_SHIFT U(14)
371#define CTR_L1IP_MASK U(0x3)
372#define CTR_IMINLINE_SHIFT U(0)
373#define CTR_IMINLINE_MASK U(0xf)
Soby Mathewc6820d12016-05-09 17:49:55 +0100374
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100375#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
Soby Mathewc6820d12016-05-09 17:49:55 +0100376
David Cunado5f55e282016-10-31 17:37:34 +0000377/* PMCR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100378#define PMCR_N_SHIFT U(11)
379#define PMCR_N_MASK U(0x1f)
David Cunado5f55e282016-10-31 17:37:34 +0000380#define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100381#define PMCR_LC_BIT (U(1) << 6)
382#define PMCR_DP_BIT (U(1) << 5)
David Cunado5f55e282016-10-31 17:37:34 +0000383
Soby Mathewc6820d12016-05-09 17:49:55 +0100384/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +0000385 * Definitions of register offsets, fields and macros for CPU system
386 * instructions.
387 ******************************************************************************/
388
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100389#define TLBI_ADDR_SHIFT U(0)
390#define TLBI_ADDR_MASK U(0xFFFFF000)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000391#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
392
393/*******************************************************************************
Soby Mathewc6820d12016-05-09 17:49:55 +0100394 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
395 * system level implementation of the Generic Timer.
396 ******************************************************************************/
Soby Mathew2d9f7952018-06-11 16:21:30 +0100397#define CNTCTLBASE_CNTFRQ U(0x0)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100398#define CNTNSAR U(0x4)
Soby Mathewc6820d12016-05-09 17:49:55 +0100399#define CNTNSAR_NS_SHIFT(x) (x)
400
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100401#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
402#define CNTACR_RPCT_SHIFT U(0x0)
403#define CNTACR_RVCT_SHIFT U(0x1)
404#define CNTACR_RFRQ_SHIFT U(0x2)
405#define CNTACR_RVOFF_SHIFT U(0x3)
406#define CNTACR_RWVT_SHIFT U(0x4)
407#define CNTACR_RWPT_SHIFT U(0x5)
Soby Mathewc6820d12016-05-09 17:49:55 +0100408
Soby Mathew2d9f7952018-06-11 16:21:30 +0100409/*******************************************************************************
410 * Definitions of register offsets in the CNTBaseN Frame of the
411 * system level implementation of the Generic Timer.
412 ******************************************************************************/
413#define CNTBASE_CNTFRQ U(0x10)
414
Soby Mathewc6820d12016-05-09 17:49:55 +0100415/* MAIR macros */
416#define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << 3))
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100417#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << 3))
Soby Mathewc6820d12016-05-09 17:49:55 +0100418
419/* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */
420#define SCR p15, 0, c1, c1, 0
421#define SCTLR p15, 0, c1, c0, 0
Etienne Carriere70a004b2017-11-05 22:56:03 +0100422#define ACTLR p15, 0, c1, c0, 1
dp-arm595d0d52017-02-08 11:51:50 +0000423#define SDCR p15, 0, c1, c3, 1
Soby Mathewc6820d12016-05-09 17:49:55 +0100424#define MPIDR p15, 0, c0, c0, 5
425#define MIDR p15, 0, c0, c0, 0
426#define VBAR p15, 0, c12, c0, 0
427#define MVBAR p15, 0, c12, c0, 1
428#define NSACR p15, 0, c1, c1, 2
429#define CPACR p15, 0, c1, c0, 2
430#define DCCIMVAC p15, 0, c7, c14, 1
431#define DCCMVAC p15, 0, c7, c10, 1
432#define DCIMVAC p15, 0, c7, c6, 1
433#define DCCISW p15, 0, c7, c14, 2
434#define DCCSW p15, 0, c7, c10, 2
435#define DCISW p15, 0, c7, c6, 2
436#define CTR p15, 0, c0, c0, 1
437#define CNTFRQ p15, 0, c14, c0, 0
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100438#define ID_PFR0 p15, 0, c0, c1, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100439#define ID_PFR1 p15, 0, c0, c1, 1
440#define MAIR0 p15, 0, c10, c2, 0
441#define MAIR1 p15, 0, c10, c2, 1
442#define TTBCR p15, 0, c2, c0, 2
443#define TTBR0 p15, 0, c2, c0, 0
444#define TTBR1 p15, 0, c2, c0, 1
445#define TLBIALL p15, 0, c8, c7, 0
446#define TLBIALLIS p15, 0, c8, c3, 0
447#define TLBIMVA p15, 0, c8, c7, 1
448#define TLBIMVAA p15, 0, c8, c7, 3
Antonio Nino Diazac998032017-02-27 17:23:54 +0000449#define TLBIMVAAIS p15, 0, c8, c3, 3
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100450#define TLBIMVAHIS p15, 4, c8, c3, 1
Antonio Nino Diazac998032017-02-27 17:23:54 +0000451#define BPIALLIS p15, 0, c7, c1, 6
Dimitris Papastamos0a4cded2018-01-02 11:37:02 +0000452#define BPIALL p15, 0, c7, c5, 6
453#define ICIALLU p15, 0, c7, c5, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100454#define HSCTLR p15, 4, c1, c0, 0
455#define HCR p15, 4, c1, c1, 0
456#define HCPTR p15, 4, c1, c1, 2
David Cunadofee86532017-04-13 22:38:29 +0100457#define HSTR p15, 4, c1, c1, 3
Soby Mathewc6820d12016-05-09 17:49:55 +0100458#define CNTHCTL p15, 4, c14, c1, 0
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000459#define CNTKCTL p15, 0, c14, c1, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100460#define VPIDR p15, 4, c0, c0, 0
461#define VMPIDR p15, 4, c0, c0, 5
462#define ISR p15, 0, c12, c1, 0
463#define CLIDR p15, 1, c0, c0, 1
464#define CSSELR p15, 2, c0, c0, 0
465#define CCSIDR p15, 1, c0, c0, 0
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100466#define HTCR p15, 4, c2, c0, 2
467#define HMAIR0 p15, 4, c10, c2, 0
Douglas Raillard77414632018-08-21 12:54:45 +0100468#define ATS1CPR p15, 0, c7, c8, 0
469#define ATS1HR p15, 4, c7, c8, 0
Yatharth Kochara9f776c2016-11-10 16:17:51 +0000470#define DBGOSDLR p14, 0, c1, c3, 4
Soby Mathewc6820d12016-05-09 17:49:55 +0100471
David Cunado5f55e282016-10-31 17:37:34 +0000472/* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
473#define HDCR p15, 4, c1, c1, 1
David Cunado5f55e282016-10-31 17:37:34 +0000474#define PMCR p15, 0, c9, c12, 0
David Cunadoc14b08e2016-11-25 00:21:59 +0000475#define CNTHP_CTL p15, 4, c14, c2, 1
David Cunado5f55e282016-10-31 17:37:34 +0000476
Etienne Carriere70a004b2017-11-05 22:56:03 +0100477/* AArch32 coproc registers for 32bit MMU descriptor support */
478#define PRRR p15, 0, c10, c2, 0
479#define NMRR p15, 0, c10, c2, 1
480#define DACR p15, 0, c3, c0, 0
481
Soby Mathewc6820d12016-05-09 17:49:55 +0100482/* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
483#define ICC_IAR1 p15, 0, c12, c12, 0
484#define ICC_IAR0 p15, 0, c12, c8, 0
485#define ICC_EOIR1 p15, 0, c12, c12, 1
486#define ICC_EOIR0 p15, 0, c12, c8, 1
487#define ICC_HPPIR1 p15, 0, c12, c12, 2
488#define ICC_HPPIR0 p15, 0, c12, c8, 2
489#define ICC_BPR1 p15, 0, c12, c12, 3
490#define ICC_BPR0 p15, 0, c12, c8, 3
491#define ICC_DIR p15, 0, c12, c11, 1
492#define ICC_PMR p15, 0, c4, c6, 0
493#define ICC_RPR p15, 0, c12, c11, 3
494#define ICC_CTLR p15, 0, c12, c12, 4
495#define ICC_MCTLR p15, 6, c12, c12, 4
496#define ICC_SRE p15, 0, c12, c12, 5
497#define ICC_HSRE p15, 4, c12, c9, 5
498#define ICC_MSRE p15, 6, c12, c12, 5
499#define ICC_IGRPEN0 p15, 0, c12, c12, 6
500#define ICC_IGRPEN1 p15, 0, c12, c12, 7
501#define ICC_MGRPEN1 p15, 6, c12, c12, 7
502
503/* 64 bit system register defines The format is: coproc, opt1, CRm */
504#define TTBR0_64 p15, 0, c2
505#define TTBR1_64 p15, 1, c2
506#define CNTVOFF_64 p15, 4, c14
507#define VTTBR_64 p15, 6, c2
508#define CNTPCT_64 p15, 0, c14
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100509#define HTTBR_64 p15, 4, c2
Douglas Raillard77414632018-08-21 12:54:45 +0100510#define PAR_64 p15, 0, c7
Soby Mathewc6820d12016-05-09 17:49:55 +0100511
512/* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */
513#define ICC_SGI1R_EL1_64 p15, 0, c12
514#define ICC_ASGI1R_EL1_64 p15, 1, c12
515#define ICC_SGI0R_EL1_64 p15, 2, c12
516
Isla Mitchell02c63072017-07-21 14:44:36 +0100517/*******************************************************************************
518 * Definitions of MAIR encodings for device and normal memory
519 ******************************************************************************/
520/*
521 * MAIR encodings for device memory attributes.
522 */
523#define MAIR_DEV_nGnRnE U(0x0)
524#define MAIR_DEV_nGnRE U(0x4)
525#define MAIR_DEV_nGRE U(0x8)
526#define MAIR_DEV_GRE U(0xc)
527
528/*
529 * MAIR encodings for normal memory attributes.
530 *
531 * Cache Policy
532 * WT: Write Through
533 * WB: Write Back
534 * NC: Non-Cacheable
535 *
536 * Transient Hint
537 * NTR: Non-Transient
538 * TR: Transient
539 *
540 * Allocation Policy
541 * RA: Read Allocate
542 * WA: Write Allocate
543 * RWA: Read and Write Allocate
544 * NA: No Allocation
545 */
546#define MAIR_NORM_WT_TR_WA U(0x1)
547#define MAIR_NORM_WT_TR_RA U(0x2)
548#define MAIR_NORM_WT_TR_RWA U(0x3)
549#define MAIR_NORM_NC U(0x4)
550#define MAIR_NORM_WB_TR_WA U(0x5)
551#define MAIR_NORM_WB_TR_RA U(0x6)
552#define MAIR_NORM_WB_TR_RWA U(0x7)
553#define MAIR_NORM_WT_NTR_NA U(0x8)
554#define MAIR_NORM_WT_NTR_WA U(0x9)
555#define MAIR_NORM_WT_NTR_RA U(0xa)
556#define MAIR_NORM_WT_NTR_RWA U(0xb)
557#define MAIR_NORM_WB_NTR_NA U(0xc)
558#define MAIR_NORM_WB_NTR_WA U(0xd)
559#define MAIR_NORM_WB_NTR_RA U(0xe)
560#define MAIR_NORM_WB_NTR_RWA U(0xf)
561
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100562#define MAIR_NORM_OUTER_SHIFT U(4)
Isla Mitchell02c63072017-07-21 14:44:36 +0100563
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100564#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
565 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
Isla Mitchell02c63072017-07-21 14:44:36 +0100566
Douglas Raillard77414632018-08-21 12:54:45 +0100567/* PAR fields */
568#define PAR_F_SHIFT U(0)
569#define PAR_F_MASK ULL(0x1)
570#define PAR_ADDR_SHIFT U(12)
Yann Gautier812c3252018-09-20 15:48:52 +0200571#define PAR_ADDR_MASK (BIT_64(40) - ULL(1)) /* 40-bits-wide page address */
Douglas Raillard77414632018-08-21 12:54:45 +0100572
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100573/*******************************************************************************
574 * Definitions for system register interface to AMU for ARMv8.4 onwards
575 ******************************************************************************/
576#define AMCR p15, 0, c13, c2, 0
577#define AMCFGR p15, 0, c13, c2, 1
578#define AMCGCR p15, 0, c13, c2, 2
579#define AMUSERENR p15, 0, c13, c2, 3
580#define AMCNTENCLR0 p15, 0, c13, c2, 4
581#define AMCNTENSET0 p15, 0, c13, c2, 5
582#define AMCNTENCLR1 p15, 0, c13, c3, 0
Joel Hutton0dcdd8d2017-12-21 15:21:20 +0000583#define AMCNTENSET1 p15, 0, c13, c3, 1
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100584
585/* Activity Monitor Group 0 Event Counter Registers */
586#define AMEVCNTR00 p15, 0, c0
587#define AMEVCNTR01 p15, 1, c0
588#define AMEVCNTR02 p15, 2, c0
589#define AMEVCNTR03 p15, 3, c0
590
591/* Activity Monitor Group 0 Event Type Registers */
592#define AMEVTYPER00 p15, 0, c13, c6, 0
593#define AMEVTYPER01 p15, 0, c13, c6, 1
594#define AMEVTYPER02 p15, 0, c13, c6, 2
595#define AMEVTYPER03 p15, 0, c13, c6, 3
596
Joel Hutton2691bc62017-12-12 15:47:55 +0000597/* Activity Monitor Group 1 Event Counter Registers */
598#define AMEVCNTR10 p15, 0, c4
599#define AMEVCNTR11 p15, 1, c4
600#define AMEVCNTR12 p15, 2, c4
601#define AMEVCNTR13 p15, 3, c4
602#define AMEVCNTR14 p15, 4, c4
603#define AMEVCNTR15 p15, 5, c4
604#define AMEVCNTR16 p15, 6, c4
605#define AMEVCNTR17 p15, 7, c4
606#define AMEVCNTR18 p15, 0, c5
607#define AMEVCNTR19 p15, 1, c5
608#define AMEVCNTR1A p15, 2, c5
609#define AMEVCNTR1B p15, 3, c5
610#define AMEVCNTR1C p15, 4, c5
611#define AMEVCNTR1D p15, 5, c5
612#define AMEVCNTR1E p15, 6, c5
613#define AMEVCNTR1F p15, 7, c5
614
615/* Activity Monitor Group 1 Event Type Registers */
616#define AMEVTYPER10 p15, 0, c13, c14, 0
617#define AMEVTYPER11 p15, 0, c13, c14, 1
618#define AMEVTYPER12 p15, 0, c13, c14, 2
619#define AMEVTYPER13 p15, 0, c13, c14, 3
620#define AMEVTYPER14 p15, 0, c13, c14, 4
621#define AMEVTYPER15 p15, 0, c13, c14, 5
622#define AMEVTYPER16 p15, 0, c13, c14, 6
623#define AMEVTYPER17 p15, 0, c13, c14, 7
624#define AMEVTYPER18 p15, 0, c13, c15, 0
625#define AMEVTYPER19 p15, 0, c13, c15, 1
626#define AMEVTYPER1A p15, 0, c13, c15, 2
627#define AMEVTYPER1B p15, 0, c13, c15, 3
628#define AMEVTYPER1C p15, 0, c13, c15, 4
629#define AMEVTYPER1D p15, 0, c13, c15, 5
630#define AMEVTYPER1E p15, 0, c13, c15, 6
631#define AMEVTYPER1F p15, 0, c13, c15, 7
632
Soby Mathewc6820d12016-05-09 17:49:55 +0100633#endif /* __ARCH_H__ */