Edward-JW Yang | 63582ec | 2021-11-01 20:20:18 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <lib/mmio.h> |
| 8 | #include <lib/utils_def.h> |
| 9 | #include <mtk_dcm_utils.h> |
| 10 | |
| 11 | #define MP_CPUSYS_TOP_ADB_DCM_REG0_MASK (BIT(16) | \ |
| 12 | BIT(17) | \ |
| 13 | BIT(18) | \ |
| 14 | BIT(21)) |
| 15 | #define MP_CPUSYS_TOP_ADB_DCM_REG1_MASK (BIT(16) | \ |
| 16 | BIT(17) | \ |
| 17 | BIT(18)) |
| 18 | #define MP_CPUSYS_TOP_ADB_DCM_REG0_ON (BIT(16) | \ |
| 19 | BIT(17) | \ |
| 20 | BIT(18) | \ |
| 21 | BIT(21)) |
| 22 | #define MP_CPUSYS_TOP_ADB_DCM_REG1_ON (BIT(16) | \ |
| 23 | BIT(17) | \ |
| 24 | BIT(18)) |
| 25 | #define MP_CPUSYS_TOP_ADB_DCM_REG0_OFF ((0x0 << 16) | \ |
| 26 | (0x0 << 17) | \ |
| 27 | (0x0 << 18) | \ |
| 28 | (0x0 << 21)) |
| 29 | #define MP_CPUSYS_TOP_ADB_DCM_REG1_OFF ((0x0 << 16) | \ |
| 30 | (0x0 << 17) | \ |
| 31 | (0x0 << 18)) |
| 32 | |
| 33 | bool dcm_mp_cpusys_top_adb_dcm_is_on(void) |
| 34 | { |
| 35 | bool ret = true; |
| 36 | |
| 37 | ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4) & |
| 38 | MP_CPUSYS_TOP_ADB_DCM_REG0_MASK) == |
| 39 | (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG0_ON); |
| 40 | ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) & |
| 41 | MP_CPUSYS_TOP_ADB_DCM_REG1_MASK) == |
| 42 | (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG1_ON); |
| 43 | |
| 44 | return ret; |
| 45 | } |
| 46 | |
| 47 | void dcm_mp_cpusys_top_adb_dcm(bool on) |
| 48 | { |
| 49 | if (on) { |
| 50 | /* TINFO = "Turn ON DCM 'mp_cpusys_top_adb_dcm'" */ |
| 51 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4, |
| 52 | MP_CPUSYS_TOP_ADB_DCM_REG0_MASK, |
| 53 | MP_CPUSYS_TOP_ADB_DCM_REG0_ON); |
| 54 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, |
| 55 | MP_CPUSYS_TOP_ADB_DCM_REG1_MASK, |
| 56 | MP_CPUSYS_TOP_ADB_DCM_REG1_ON); |
| 57 | } else { |
| 58 | /* TINFO = "Turn OFF DCM 'mp_cpusys_top_adb_dcm'" */ |
| 59 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4, |
| 60 | MP_CPUSYS_TOP_ADB_DCM_REG0_MASK, |
| 61 | MP_CPUSYS_TOP_ADB_DCM_REG0_OFF); |
| 62 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, |
| 63 | MP_CPUSYS_TOP_ADB_DCM_REG1_MASK, |
| 64 | MP_CPUSYS_TOP_ADB_DCM_REG1_OFF); |
| 65 | } |
| 66 | } |
| 67 | |
| 68 | #define MP_CPUSYS_TOP_APB_DCM_REG0_MASK (BIT(5)) |
| 69 | #define MP_CPUSYS_TOP_APB_DCM_REG1_MASK (BIT(8)) |
| 70 | #define MP_CPUSYS_TOP_APB_DCM_REG2_MASK (BIT(16)) |
| 71 | #define MP_CPUSYS_TOP_APB_DCM_REG0_ON (BIT(5)) |
| 72 | #define MP_CPUSYS_TOP_APB_DCM_REG1_ON (BIT(8)) |
| 73 | #define MP_CPUSYS_TOP_APB_DCM_REG2_ON (BIT(16)) |
| 74 | #define MP_CPUSYS_TOP_APB_DCM_REG0_OFF ((0x0 << 5)) |
| 75 | #define MP_CPUSYS_TOP_APB_DCM_REG1_OFF ((0x0 << 8)) |
| 76 | #define MP_CPUSYS_TOP_APB_DCM_REG2_OFF ((0x0 << 16)) |
| 77 | |
| 78 | bool dcm_mp_cpusys_top_apb_dcm_is_on(void) |
| 79 | { |
| 80 | bool ret = true; |
| 81 | |
| 82 | ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) & |
| 83 | MP_CPUSYS_TOP_APB_DCM_REG0_MASK) == |
| 84 | (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG0_ON); |
| 85 | ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) & |
| 86 | MP_CPUSYS_TOP_APB_DCM_REG1_MASK) == |
| 87 | (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG1_ON); |
| 88 | ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG0) & |
| 89 | MP_CPUSYS_TOP_APB_DCM_REG2_MASK) == |
| 90 | (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG2_ON); |
| 91 | |
| 92 | return ret; |
| 93 | } |
| 94 | |
| 95 | void dcm_mp_cpusys_top_apb_dcm(bool on) |
| 96 | { |
| 97 | if (on) { |
| 98 | /* TINFO = "Turn ON DCM 'mp_cpusys_top_apb_dcm'" */ |
| 99 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, |
| 100 | MP_CPUSYS_TOP_APB_DCM_REG0_MASK, |
| 101 | MP_CPUSYS_TOP_APB_DCM_REG0_ON); |
| 102 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, |
| 103 | MP_CPUSYS_TOP_APB_DCM_REG1_MASK, |
| 104 | MP_CPUSYS_TOP_APB_DCM_REG1_ON); |
| 105 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, |
| 106 | MP_CPUSYS_TOP_APB_DCM_REG2_MASK, |
| 107 | MP_CPUSYS_TOP_APB_DCM_REG2_ON); |
| 108 | } else { |
| 109 | /* TINFO = "Turn OFF DCM 'mp_cpusys_top_apb_dcm'" */ |
| 110 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, |
| 111 | MP_CPUSYS_TOP_APB_DCM_REG0_MASK, |
| 112 | MP_CPUSYS_TOP_APB_DCM_REG0_OFF); |
| 113 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, |
| 114 | MP_CPUSYS_TOP_APB_DCM_REG1_MASK, |
| 115 | MP_CPUSYS_TOP_APB_DCM_REG1_OFF); |
| 116 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, |
| 117 | MP_CPUSYS_TOP_APB_DCM_REG2_MASK, |
| 118 | MP_CPUSYS_TOP_APB_DCM_REG2_OFF); |
| 119 | } |
| 120 | } |
| 121 | |
| 122 | #define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK (BIT(11) | \ |
| 123 | BIT(24) | \ |
| 124 | BIT(25)) |
| 125 | #define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON (BIT(11) | \ |
| 126 | BIT(24) | \ |
| 127 | BIT(25)) |
| 128 | #define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF ((0x0 << 11) | \ |
| 129 | (0x0 << 24) | \ |
| 130 | (0x0 << 25)) |
| 131 | |
| 132 | bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void) |
| 133 | { |
| 134 | bool ret = true; |
| 135 | |
| 136 | ret &= ((mmio_read_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG) & |
| 137 | MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK) == |
| 138 | (unsigned int) MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON); |
| 139 | |
| 140 | return ret; |
| 141 | } |
| 142 | |
| 143 | void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on) |
| 144 | { |
| 145 | if (on) { |
| 146 | /* TINFO = "Turn ON DCM 'mp_cpusys_top_bus_pll_div_dcm'" */ |
| 147 | mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG, |
| 148 | MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK, |
| 149 | MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON); |
| 150 | } else { |
| 151 | /* TINFO = "Turn OFF DCM 'mp_cpusys_top_bus_pll_div_dcm'" */ |
| 152 | mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG, |
| 153 | MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK, |
| 154 | MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF); |
| 155 | } |
| 156 | } |
| 157 | |
| 158 | #define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK (BIT(0)) |
| 159 | #define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON (BIT(0)) |
| 160 | #define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF ((0x0 << 0)) |
| 161 | |
| 162 | bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void) |
| 163 | { |
| 164 | bool ret = true; |
| 165 | |
| 166 | ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG7) & |
| 167 | MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK) == |
| 168 | (unsigned int) MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON); |
| 169 | |
| 170 | return ret; |
| 171 | } |
| 172 | |
| 173 | void dcm_mp_cpusys_top_core_stall_dcm(bool on) |
| 174 | { |
| 175 | if (on) { |
| 176 | /* TINFO = "Turn ON DCM 'mp_cpusys_top_core_stall_dcm'" */ |
| 177 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7, |
| 178 | MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK, |
| 179 | MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON); |
| 180 | } else { |
| 181 | /* TINFO = "Turn OFF DCM 'mp_cpusys_top_core_stall_dcm'" */ |
| 182 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7, |
| 183 | MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK, |
| 184 | MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF); |
| 185 | } |
| 186 | } |
| 187 | |
| 188 | #define MP_CPUSYS_TOP_CPUBIU_DBG_CG_REG0_MASK (BIT(0)) |
| 189 | #define MP_CPUSYS_TOP_CPUBIU_DBG_CG_REG0_ON ((0x0 << 0)) |
| 190 | #define MP_CPUSYS_TOP_CPUBIU_DBG_CG_REG0_OFF (BIT(0)) |
| 191 | |
| 192 | bool dcm_mp_cpusys_top_cpubiu_dbg_cg_is_on(void) |
| 193 | { |
| 194 | bool ret = true; |
| 195 | |
| 196 | ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCSI_CFG2) & |
| 197 | MP_CPUSYS_TOP_CPUBIU_DBG_CG_REG0_MASK) == |
| 198 | (unsigned int) MP_CPUSYS_TOP_CPUBIU_DBG_CG_REG0_ON); |
| 199 | |
| 200 | return ret; |
| 201 | } |
| 202 | |
| 203 | void dcm_mp_cpusys_top_cpubiu_dbg_cg(bool on) |
| 204 | { |
| 205 | if (on) { |
| 206 | /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpubiu_dbg_cg'" */ |
| 207 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MCSI_CFG2, |
| 208 | MP_CPUSYS_TOP_CPUBIU_DBG_CG_REG0_MASK, |
| 209 | MP_CPUSYS_TOP_CPUBIU_DBG_CG_REG0_ON); |
| 210 | } else { |
| 211 | /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpubiu_dbg_cg'" */ |
| 212 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MCSI_CFG2, |
| 213 | MP_CPUSYS_TOP_CPUBIU_DBG_CG_REG0_MASK, |
| 214 | MP_CPUSYS_TOP_CPUBIU_DBG_CG_REG0_OFF); |
| 215 | } |
| 216 | } |
| 217 | |
| 218 | #define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK ((0xffff << 0)) |
| 219 | #define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON ((0xffff << 0)) |
| 220 | #define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF ((0x0 << 0)) |
| 221 | |
| 222 | bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void) |
| 223 | { |
| 224 | bool ret = true; |
| 225 | |
| 226 | ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCSIC_DCM0) & |
| 227 | MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK) == |
| 228 | (unsigned int) MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON); |
| 229 | |
| 230 | return ret; |
| 231 | } |
| 232 | |
| 233 | void dcm_mp_cpusys_top_cpubiu_dcm(bool on) |
| 234 | { |
| 235 | if (on) { |
| 236 | /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpubiu_dcm'" */ |
| 237 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MCSIC_DCM0, |
| 238 | MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK, |
| 239 | MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON); |
| 240 | } else { |
| 241 | /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpubiu_dcm'" */ |
| 242 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MCSIC_DCM0, |
| 243 | MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK, |
| 244 | MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF); |
| 245 | } |
| 246 | } |
| 247 | |
| 248 | #define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK (BIT(11) | \ |
| 249 | BIT(24) | \ |
| 250 | BIT(25)) |
| 251 | #define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON (BIT(11) | \ |
| 252 | BIT(24) | \ |
| 253 | BIT(25)) |
| 254 | #define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF ((0x0 << 11) | \ |
| 255 | (0x0 << 24) | \ |
| 256 | (0x0 << 25)) |
| 257 | |
| 258 | bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void) |
| 259 | { |
| 260 | bool ret = true; |
| 261 | |
| 262 | ret &= ((mmio_read_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0) & |
| 263 | MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK) == |
| 264 | (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON); |
| 265 | |
| 266 | return ret; |
| 267 | } |
| 268 | |
| 269 | void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on) |
| 270 | { |
| 271 | if (on) { |
| 272 | /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */ |
| 273 | mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0, |
| 274 | MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK, |
| 275 | MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON); |
| 276 | } else { |
| 277 | /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */ |
| 278 | mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0, |
| 279 | MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK, |
| 280 | MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF); |
| 281 | } |
| 282 | } |
| 283 | |
| 284 | #define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK (BIT(11) | \ |
| 285 | BIT(24) | \ |
| 286 | BIT(25)) |
| 287 | #define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON (BIT(11) | \ |
| 288 | BIT(24) | \ |
| 289 | BIT(25)) |
| 290 | #define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF ((0x0 << 11) | \ |
| 291 | (0x0 << 24) | \ |
| 292 | (0x0 << 25)) |
| 293 | |
| 294 | bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void) |
| 295 | { |
| 296 | bool ret = true; |
| 297 | |
| 298 | ret &= ((mmio_read_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1) & |
| 299 | MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK) == |
| 300 | (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON); |
| 301 | |
| 302 | return ret; |
| 303 | } |
| 304 | |
| 305 | void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on) |
| 306 | { |
| 307 | if (on) { |
| 308 | /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */ |
| 309 | mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1, |
| 310 | MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK, |
| 311 | MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON); |
| 312 | } else { |
| 313 | /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */ |
| 314 | mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1, |
| 315 | MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK, |
| 316 | MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF); |
| 317 | } |
| 318 | } |
| 319 | |
| 320 | #define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK (BIT(4)) |
| 321 | #define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON (BIT(4)) |
| 322 | #define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF ((0x0 << 4)) |
| 323 | |
| 324 | bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void) |
| 325 | { |
| 326 | bool ret = true; |
| 327 | |
| 328 | ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG7) & |
| 329 | MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK) == |
| 330 | (unsigned int) MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON); |
| 331 | |
| 332 | return ret; |
| 333 | } |
| 334 | |
| 335 | void dcm_mp_cpusys_top_fcm_stall_dcm(bool on) |
| 336 | { |
| 337 | if (on) { |
| 338 | /* TINFO = "Turn ON DCM 'mp_cpusys_top_fcm_stall_dcm'" */ |
| 339 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7, |
| 340 | MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK, |
| 341 | MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON); |
| 342 | } else { |
| 343 | /* TINFO = "Turn OFF DCM 'mp_cpusys_top_fcm_stall_dcm'" */ |
| 344 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7, |
| 345 | MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK, |
| 346 | MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF); |
| 347 | } |
| 348 | } |
| 349 | |
| 350 | #define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK (BIT(31)) |
| 351 | #define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON (BIT(31)) |
| 352 | #define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF ((0x0 << 31)) |
| 353 | |
| 354 | bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void) |
| 355 | { |
| 356 | bool ret = true; |
| 357 | |
| 358 | ret &= ((mmio_read_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG) & |
| 359 | MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK) == |
| 360 | (unsigned int) MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON); |
| 361 | |
| 362 | return ret; |
| 363 | } |
| 364 | |
| 365 | void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on) |
| 366 | { |
| 367 | if (on) { |
| 368 | /* TINFO = "Turn ON DCM 'mp_cpusys_top_last_cor_idle_dcm'" */ |
| 369 | mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG, |
| 370 | MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK, |
| 371 | MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON); |
| 372 | } else { |
| 373 | /* TINFO = "Turn OFF DCM 'mp_cpusys_top_last_cor_idle_dcm'" */ |
| 374 | mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG, |
| 375 | MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK, |
| 376 | MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF); |
| 377 | } |
| 378 | } |
| 379 | |
| 380 | #define MP_CPUSYS_TOP_MISC_DCM_REG0_MASK (BIT(0) | \ |
| 381 | BIT(1) | \ |
| 382 | BIT(2) | \ |
| 383 | BIT(3) | \ |
| 384 | BIT(4)) |
| 385 | #define MP_CPUSYS_TOP_MISC_DCM_REG0_ON (BIT(0) | \ |
| 386 | BIT(1) | \ |
| 387 | BIT(2) | \ |
| 388 | BIT(3) | \ |
| 389 | BIT(4)) |
| 390 | #define MP_CPUSYS_TOP_MISC_DCM_REG0_OFF ((0x0 << 0) | \ |
| 391 | (0x0 << 1) | \ |
| 392 | (0x0 << 2) | \ |
| 393 | (0x0 << 3) | \ |
| 394 | (0x0 << 4)) |
| 395 | |
| 396 | bool dcm_mp_cpusys_top_misc_dcm_is_on(void) |
| 397 | { |
| 398 | bool ret = true; |
| 399 | |
| 400 | ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) & |
| 401 | MP_CPUSYS_TOP_MISC_DCM_REG0_MASK) == |
| 402 | (unsigned int) MP_CPUSYS_TOP_MISC_DCM_REG0_ON); |
| 403 | |
| 404 | return ret; |
| 405 | } |
| 406 | |
| 407 | void dcm_mp_cpusys_top_misc_dcm(bool on) |
| 408 | { |
| 409 | if (on) { |
| 410 | /* TINFO = "Turn ON DCM 'mp_cpusys_top_misc_dcm'" */ |
| 411 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, |
| 412 | MP_CPUSYS_TOP_MISC_DCM_REG0_MASK, |
| 413 | MP_CPUSYS_TOP_MISC_DCM_REG0_ON); |
| 414 | } else { |
| 415 | /* TINFO = "Turn OFF DCM 'mp_cpusys_top_misc_dcm'" */ |
| 416 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, |
| 417 | MP_CPUSYS_TOP_MISC_DCM_REG0_MASK, |
| 418 | MP_CPUSYS_TOP_MISC_DCM_REG0_OFF); |
| 419 | } |
| 420 | } |
| 421 | |
| 422 | #define MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK (BIT(0) | \ |
| 423 | BIT(1) | \ |
| 424 | BIT(2) | \ |
| 425 | BIT(3)) |
| 426 | #define MP_CPUSYS_TOP_MP0_QDCM_REG0_ON (BIT(0) | \ |
| 427 | BIT(1) | \ |
| 428 | BIT(2) | \ |
| 429 | BIT(3)) |
| 430 | #define MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF ((0x0 << 0) | \ |
| 431 | (0x0 << 1) | \ |
| 432 | (0x0 << 2) | \ |
| 433 | (0x0 << 3)) |
| 434 | |
| 435 | bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void) |
| 436 | { |
| 437 | bool ret = true; |
| 438 | |
| 439 | ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG0) & |
| 440 | MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK) == |
| 441 | (unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG0_ON); |
| 442 | |
| 443 | return ret; |
| 444 | } |
| 445 | |
| 446 | void dcm_mp_cpusys_top_mp0_qdcm(bool on) |
| 447 | { |
| 448 | if (on) { |
| 449 | /* TINFO = "Turn ON DCM 'mp_cpusys_top_mp0_qdcm'" */ |
| 450 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, |
| 451 | MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK, |
| 452 | MP_CPUSYS_TOP_MP0_QDCM_REG0_ON); |
| 453 | } else { |
| 454 | /* TINFO = "Turn OFF DCM 'mp_cpusys_top_mp0_qdcm'" */ |
| 455 | mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, |
| 456 | MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK, |
| 457 | MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF); |
| 458 | } |
| 459 | } |
| 460 | |
| 461 | #define CPCCFG_REG_EMI_WFIFO_REG0_MASK (BIT(0) | BIT(2)) |
| 462 | #define CPCCFG_REG_EMI_WFIFO_REG0_ON (BIT(0) | BIT(2)) |
| 463 | #define CPCCFG_REG_EMI_WFIFO_REG0_OFF ((0x0 << 0) | (0x0 << 2)) |
| 464 | |
| 465 | bool dcm_cpccfg_reg_emi_wfifo_is_on(void) |
| 466 | { |
| 467 | bool ret = true; |
| 468 | |
| 469 | ret &= ((mmio_read_32(CPCCFG_REG_EMI_WFIFO) & |
| 470 | CPCCFG_REG_EMI_WFIFO_REG0_MASK) == |
| 471 | (unsigned int) CPCCFG_REG_EMI_WFIFO_REG0_ON); |
| 472 | |
| 473 | return ret; |
| 474 | } |
| 475 | |
| 476 | void dcm_cpccfg_reg_emi_wfifo(bool on) |
| 477 | { |
| 478 | if (on) { |
| 479 | /* TINFO = "Turn ON DCM 'cpccfg_reg_emi_wfifo'" */ |
| 480 | mmio_clrsetbits_32(CPCCFG_REG_EMI_WFIFO, |
| 481 | CPCCFG_REG_EMI_WFIFO_REG0_MASK, |
| 482 | CPCCFG_REG_EMI_WFIFO_REG0_ON); |
| 483 | } else { |
| 484 | /* TINFO = "Turn OFF DCM 'cpccfg_reg_emi_wfifo'" */ |
| 485 | mmio_clrsetbits_32(CPCCFG_REG_EMI_WFIFO, |
| 486 | CPCCFG_REG_EMI_WFIFO_REG0_MASK, |
| 487 | CPCCFG_REG_EMI_WFIFO_REG0_OFF); |
| 488 | } |
| 489 | } |
| 490 | |