Lad Prabhakar | 84e942d | 2020-12-21 11:33:16 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <stdint.h> |
| 8 | |
| 9 | #include <common/debug.h> |
| 10 | #include <lib/mmio.h> |
| 11 | |
| 12 | #include "qos_init_g2e_v10.h" |
| 13 | #include "../qos_common.h" |
| 14 | #include "../qos_reg.h" |
| 15 | |
| 16 | #define RCAR_QOS_VERSION "rev.0.05" |
| 17 | |
| 18 | #define REF_ARS_ARBSTOPCYCLE_G2E (((SL_INIT_SSLOTCLK_G2E) - 5U) << 16U) |
| 19 | |
| 20 | #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT |
| 21 | #if RCAR_REF_INT == RCAR_REF_DEFAULT |
| 22 | #include "qos_init_g2e_v10_mstat390.h" |
| 23 | #else |
| 24 | #include "qos_init_g2e_v10_mstat780.h" |
| 25 | #endif /* RCAR_REF_INT == RCAR_REF_DEFAULT */ |
| 26 | #endif /* RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT */ |
| 27 | |
| 28 | static const struct rcar_gen3_dbsc_qos_settings g2e_qos[] = { |
| 29 | /* BUFCAM settings */ |
| 30 | { DBSC_DBCAM0CNF1, 0x00043218U }, |
| 31 | { DBSC_DBCAM0CNF2, 0x000000F4U }, |
| 32 | { DBSC_DBSCHCNT0, 0x000F0037U }, |
| 33 | { DBSC_DBSCHSZ0, 0x00000001U }, |
| 34 | { DBSC_DBSCHRW0, 0x22421111U }, |
| 35 | |
| 36 | /* DDR3 */ |
| 37 | { DBSC_SCFCTST2, 0x012F1123U }, |
| 38 | |
| 39 | /* QoS Settings */ |
| 40 | { DBSC_DBSCHQOS00, 0x00000F00U }, |
| 41 | { DBSC_DBSCHQOS01, 0x00000B00U }, |
| 42 | { DBSC_DBSCHQOS02, 0x00000000U }, |
| 43 | { DBSC_DBSCHQOS03, 0x00000000U }, |
| 44 | { DBSC_DBSCHQOS40, 0x00000300U }, |
| 45 | { DBSC_DBSCHQOS41, 0x000002F0U }, |
| 46 | { DBSC_DBSCHQOS42, 0x00000200U }, |
| 47 | { DBSC_DBSCHQOS43, 0x00000100U }, |
| 48 | { DBSC_DBSCHQOS90, 0x00000100U }, |
| 49 | { DBSC_DBSCHQOS91, 0x000000F0U }, |
| 50 | { DBSC_DBSCHQOS92, 0x000000A0U }, |
| 51 | { DBSC_DBSCHQOS93, 0x00000040U }, |
| 52 | { DBSC_DBSCHQOS130, 0x00000100U }, |
| 53 | { DBSC_DBSCHQOS131, 0x000000F0U }, |
| 54 | { DBSC_DBSCHQOS132, 0x000000A0U }, |
| 55 | { DBSC_DBSCHQOS133, 0x00000040U }, |
| 56 | { DBSC_DBSCHQOS140, 0x000000C0U }, |
| 57 | { DBSC_DBSCHQOS141, 0x000000B0U }, |
| 58 | { DBSC_DBSCHQOS142, 0x00000080U }, |
| 59 | { DBSC_DBSCHQOS143, 0x00000040U }, |
| 60 | { DBSC_DBSCHQOS150, 0x00000040U }, |
| 61 | { DBSC_DBSCHQOS151, 0x00000030U }, |
| 62 | { DBSC_DBSCHQOS152, 0x00000020U }, |
| 63 | { DBSC_DBSCHQOS153, 0x00000010U }, |
| 64 | }; |
| 65 | |
| 66 | void qos_init_g2e_v10(void) |
| 67 | { |
| 68 | rzg_qos_dbsc_setting(g2e_qos, ARRAY_SIZE(g2e_qos), true); |
| 69 | |
| 70 | /* DRAM Split Address mapping */ |
| 71 | #if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH |
| 72 | #if RCAR_LSI == RCAR_RZ_G2E |
| 73 | #error "Don't set DRAM Split 4ch(G2E)" |
| 74 | #else |
| 75 | ERROR("DRAM Split 4ch not supported.(G2E)"); |
| 76 | panic(); |
| 77 | #endif |
| 78 | #elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) |
| 79 | #if RCAR_LSI == RCAR_RZ_G2E |
| 80 | #error "Don't set DRAM Split 2ch(G2E)" |
| 81 | #else |
| 82 | ERROR("DRAM Split 2ch not supported.(G2E)"); |
| 83 | panic(); |
| 84 | #endif |
| 85 | #else |
| 86 | NOTICE("BL2: DRAM Split is OFF\n"); |
| 87 | #endif |
| 88 | |
| 89 | #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) |
| 90 | #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT |
| 91 | NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); |
| 92 | #endif |
| 93 | |
| 94 | #if RCAR_REF_INT == RCAR_REF_DEFAULT |
| 95 | NOTICE("BL2: DRAM refresh interval 3.9 usec\n"); |
| 96 | #else |
| 97 | NOTICE("BL2: DRAM refresh interval 7.8 usec\n"); |
| 98 | #endif |
| 99 | |
| 100 | mmio_write_32(QOSCTRL_RAS, 0x00000020U); |
| 101 | mmio_write_64(QOSCTRL_DANN, 0x0404020002020201UL); |
| 102 | mmio_write_32(QOSCTRL_DANT, 0x00100804U); |
| 103 | mmio_write_32(QOSCTRL_FSS, 0x0000000AU); |
| 104 | mmio_write_32(QOSCTRL_INSFC, 0x06330001U); |
| 105 | mmio_write_32(QOSCTRL_EARLYR, 0x00000000U); |
| 106 | mmio_write_32(QOSCTRL_RACNT0, 0x00010003U); |
| 107 | |
| 108 | mmio_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT | |
| 109 | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_G2E); |
| 110 | mmio_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_G2E); |
| 111 | |
| 112 | /* QOSBW SRAM setting */ |
| 113 | uint32_t i; |
| 114 | |
| 115 | for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { |
| 116 | mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]); |
| 117 | mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]); |
| 118 | } |
| 119 | for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { |
| 120 | mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]); |
| 121 | mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]); |
| 122 | } |
| 123 | |
| 124 | /* RT bus Leaf setting */ |
| 125 | mmio_write_32(RT_ACT0, 0x00000000U); |
| 126 | mmio_write_32(RT_ACT1, 0x00000000U); |
| 127 | |
| 128 | /* CCI bus Leaf setting */ |
| 129 | mmio_write_32(CPU_ACT0, 0x00000003U); |
| 130 | mmio_write_32(CPU_ACT1, 0x00000003U); |
| 131 | |
| 132 | mmio_write_32(QOSCTRL_RAEN, 0x00000001U); |
| 133 | |
| 134 | mmio_write_32(QOSCTRL_STATQC, 0x00000001U); |
| 135 | #else |
| 136 | NOTICE("BL2: QoS is None\n"); |
| 137 | |
| 138 | mmio_write_32(QOSCTRL_RAEN, 0x00000001U); |
| 139 | #endif |
| 140 | } |