blob: 88750d7719ffddf1061464d2050163e6dd1cb5aa [file] [log] [blame]
Hadi Asyrafi616da772019-06-27 11:34:03 +08001/*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <common/debug.h>
9#include <common/runtime_svc.h>
10#include <tools_share/uuid.h>
11
Hadi Asyrafi6f8a2b22019-10-23 18:34:14 +080012#include "socfpga_mailbox.h"
Hadi Asyrafi616da772019-06-27 11:34:03 +080013
14/* Number of SiP Calls implemented */
15#define SIP_NUM_CALLS 0x3
16
17/* Total buffer the driver can hold */
18#define FPGA_CONFIG_BUFFER_SIZE 4
19
20int current_block;
21int current_buffer;
22int current_id = 1;
23int max_blocks;
24uint32_t bytes_per_block;
25uint32_t blocks_submitted;
26uint32_t blocks_completed;
27
28struct fpga_config_info {
29 uint32_t addr;
30 int size;
31 int size_written;
32 uint32_t write_requested;
33 int subblocks_sent;
34 int block_number;
35};
36
37/* SiP Service UUID */
38DEFINE_SVC_UUID2(intl_svc_uid,
39 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a,
40 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81);
41
42uint64_t socfpga_sip_handler(uint32_t smc_fid,
43 uint64_t x1,
44 uint64_t x2,
45 uint64_t x3,
46 uint64_t x4,
47 void *cookie,
48 void *handle,
49 uint64_t flags)
50{
51 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
52 SMC_RET1(handle, SMC_UNK);
53}
54
55struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE];
56
57static void intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer)
58{
59 uint32_t args[3];
60
61 while (max_blocks > 0 && buffer->size > buffer->size_written) {
62 if (buffer->size - buffer->size_written <=
63 bytes_per_block) {
64 args[0] = (1<<8);
65 args[1] = buffer->addr + buffer->size_written;
66 args[2] = buffer->size - buffer->size_written;
67 buffer->size_written +=
68 buffer->size - buffer->size_written;
69 buffer->subblocks_sent++;
70 mailbox_send_cmd_async(0x4,
71 MBOX_RECONFIG_DATA,
72 args, 3, 0);
73 current_buffer++;
74 current_buffer %= FPGA_CONFIG_BUFFER_SIZE;
75 } else {
76 args[0] = (1<<8);
77 args[1] = buffer->addr + buffer->size_written;
78 args[2] = bytes_per_block;
79 buffer->size_written += bytes_per_block;
80 mailbox_send_cmd_async(0x4,
81 MBOX_RECONFIG_DATA,
82 args, 3, 0);
83 buffer->subblocks_sent++;
84 }
85 max_blocks--;
86 }
87}
88
89static int intel_fpga_sdm_write_all(void)
90{
91 int i;
92
93 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++)
94 intel_fpga_sdm_write_buffer(
95 &fpga_config_buffers[current_buffer]);
96
97 return 0;
98}
99
100uint32_t intel_mailbox_fpga_config_isdone(void)
101{
102 uint32_t args[2];
103 uint32_t response[6];
104 int status;
105
106 status = mailbox_send_cmd(1, MBOX_RECONFIG_STATUS, args, 0, 0,
107 response);
108
109 if (status < 0)
110 return INTEL_SIP_SMC_STATUS_ERROR;
111
112 if (response[RECONFIG_STATUS_STATE] &&
113 response[RECONFIG_STATUS_STATE] != MBOX_CFGSTAT_STATE_CONFIG)
114 return INTEL_SIP_SMC_STATUS_ERROR;
115
116 if (!(response[RECONFIG_STATUS_PIN_STATUS] & PIN_STATUS_NSTATUS))
117 return INTEL_SIP_SMC_STATUS_ERROR;
118
119 if (response[RECONFIG_STATUS_SOFTFUNC_STATUS] &
120 SOFTFUNC_STATUS_SEU_ERROR)
121 return INTEL_SIP_SMC_STATUS_ERROR;
122
123 if ((response[RECONFIG_STATUS_SOFTFUNC_STATUS] &
124 SOFTFUNC_STATUS_CONF_DONE) &&
125 (response[RECONFIG_STATUS_SOFTFUNC_STATUS] &
126 SOFTFUNC_STATUS_INIT_DONE))
127 return INTEL_SIP_SMC_STATUS_OK;
128
129 return INTEL_SIP_SMC_STATUS_ERROR;
130}
131
132static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed)
133{
134 int i;
135
136 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
137 if (fpga_config_buffers[i].block_number == current_block) {
138 fpga_config_buffers[i].subblocks_sent--;
139 if (fpga_config_buffers[i].subblocks_sent == 0
140 && fpga_config_buffers[i].size <=
141 fpga_config_buffers[i].size_written) {
142 fpga_config_buffers[i].write_requested = 0;
143 current_block++;
144 *buffer_addr_completed =
145 fpga_config_buffers[i].addr;
146 return 0;
147 }
148 }
149 }
150
151 return -1;
152}
153
154unsigned int address_in_ddr(uint32_t *addr)
155{
156 if (((unsigned long long)addr > DRAM_BASE) &&
157 ((unsigned long long)addr < DRAM_BASE + DRAM_SIZE))
158 return 0;
159
160 return -1;
161}
162
163int intel_fpga_config_completed_write(uint32_t *completed_addr,
164 uint32_t *count)
165{
166 uint32_t status = INTEL_SIP_SMC_STATUS_OK;
167 *count = 0;
168 int resp_len = 0;
169 uint32_t resp[5];
170 int all_completed = 1;
171 int count_check = 0;
172
173 if (address_in_ddr(completed_addr) != 0 || address_in_ddr(count) != 0)
174 return INTEL_SIP_SMC_STATUS_ERROR;
175
176 for (count_check = 0; count_check < 3; count_check++)
177 if (address_in_ddr(&completed_addr[*count + count_check]) != 0)
178 return INTEL_SIP_SMC_STATUS_ERROR;
179
180 resp_len = mailbox_read_response(0x4, resp);
181
182 while (resp_len >= 0 && *count < 3) {
183 max_blocks++;
184 if (mark_last_buffer_xfer_completed(
185 &completed_addr[*count]) == 0)
186 *count = *count + 1;
187 else
188 break;
189 resp_len = mailbox_read_response(0x4, resp);
190 }
191
192 if (*count <= 0) {
193 if (resp_len != MBOX_NO_RESPONSE &&
194 resp_len != MBOX_TIMEOUT && resp_len != 0) {
195 return INTEL_SIP_SMC_STATUS_ERROR;
196 }
197
198 *count = 0;
199 }
200
201 intel_fpga_sdm_write_all();
202
203 if (*count > 0)
204 status = INTEL_SIP_SMC_STATUS_OK;
205 else if (*count == 0)
206 status = INTEL_SIP_SMC_STATUS_BUSY;
207
208 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
209 if (fpga_config_buffers[i].write_requested != 0) {
210 all_completed = 0;
211 break;
212 }
213 }
214
215 if (all_completed == 1)
216 return INTEL_SIP_SMC_STATUS_OK;
217
218 return status;
219}
220
221int intel_fpga_config_start(uint32_t config_type)
222{
223 uint32_t response[3];
224 int status = 0;
225
226 status = mailbox_send_cmd(2, MBOX_RECONFIG, 0, 0, 0,
227 response);
228
229 if (status < 0)
230 return status;
231
232 max_blocks = response[0];
233 bytes_per_block = response[1];
234
235 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
236 fpga_config_buffers[i].size = 0;
237 fpga_config_buffers[i].size_written = 0;
238 fpga_config_buffers[i].addr = 0;
239 fpga_config_buffers[i].write_requested = 0;
240 fpga_config_buffers[i].block_number = 0;
241 fpga_config_buffers[i].subblocks_sent = 0;
242 }
243
244 blocks_submitted = 0;
245 current_block = 0;
246 current_buffer = 0;
247
248 return 0;
249}
250
251
252uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size)
253{
254 int i = 0;
255 uint32_t status = INTEL_SIP_SMC_STATUS_OK;
256
257 if (mem < DRAM_BASE || mem > DRAM_BASE + DRAM_SIZE)
258 status = INTEL_SIP_SMC_STATUS_REJECTED;
259
260 if (mem + size > DRAM_BASE + DRAM_SIZE)
261 status = INTEL_SIP_SMC_STATUS_REJECTED;
262
263 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
264 if (!fpga_config_buffers[i].write_requested) {
265 fpga_config_buffers[i].addr = mem;
266 fpga_config_buffers[i].size = size;
267 fpga_config_buffers[i].size_written = 0;
268 fpga_config_buffers[i].write_requested = 1;
269 fpga_config_buffers[i].block_number =
270 blocks_submitted++;
271 fpga_config_buffers[i].subblocks_sent = 0;
272 break;
273 }
274 }
275
276
277 if (i == FPGA_CONFIG_BUFFER_SIZE) {
278 status = INTEL_SIP_SMC_STATUS_REJECTED;
279 return status;
280 } else if (i == FPGA_CONFIG_BUFFER_SIZE - 1) {
281 status = INTEL_SIP_SMC_STATUS_BUSY;
282 }
283
284 intel_fpga_sdm_write_all();
285
286 return status;
287}
288
289/*
290 * This function is responsible for handling all SiP calls from the NS world
291 */
292
293uintptr_t sip_smc_handler(uint32_t smc_fid,
294 u_register_t x1,
295 u_register_t x2,
296 u_register_t x3,
297 u_register_t x4,
298 void *cookie,
299 void *handle,
300 u_register_t flags)
301{
302 uint32_t status = INTEL_SIP_SMC_STATUS_OK;
303 uint32_t completed_addr[3];
304 uint32_t count = 0;
305
306 switch (smc_fid) {
307 case SIP_SVC_UID:
308 /* Return UID to the caller */
309 SMC_UUID_RET(handle, intl_svc_uid);
310 break;
311 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE:
312 status = intel_mailbox_fpga_config_isdone();
313 SMC_RET4(handle, status, 0, 0, 0);
314 break;
315 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM:
316 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
317 INTEL_SIP_SMC_FPGA_CONFIG_ADDR,
318 INTEL_SIP_SMC_FPGA_CONFIG_SIZE -
319 INTEL_SIP_SMC_FPGA_CONFIG_ADDR);
320 break;
321 case INTEL_SIP_SMC_FPGA_CONFIG_START:
322 status = intel_fpga_config_start(x1);
323 SMC_RET4(handle, status, 0, 0, 0);
324 break;
325 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE:
326 status = intel_fpga_config_write(x1, x2);
327 SMC_RET4(handle, status, 0, 0, 0);
328 break;
329 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE:
330 status = intel_fpga_config_completed_write(completed_addr,
331 &count);
332 switch (count) {
333 case 1:
334 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
335 completed_addr[0], 0, 0);
336 break;
337 case 2:
338 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
339 completed_addr[0],
340 completed_addr[1], 0);
341 break;
342 case 3:
343 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
344 completed_addr[0],
345 completed_addr[1],
346 completed_addr[2]);
347 break;
348 case 0:
349 SMC_RET4(handle, status, 0, 0, 0);
350 break;
351 default:
352 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
353 }
354 break;
355
356 default:
357 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
358 cookie, handle, flags);
359 }
360}
361
362DECLARE_RT_SVC(
Hadi Asyrafi4d9f3952019-10-23 17:35:32 +0800363 socfpga_sip_svc,
Hadi Asyrafi616da772019-06-27 11:34:03 +0800364 OEN_SIP_START,
365 OEN_SIP_END,
366 SMC_TYPE_FAST,
367 NULL,
368 sip_smc_handler
369);
370
371DECLARE_RT_SVC(
Hadi Asyrafi4d9f3952019-10-23 17:35:32 +0800372 socfpga_sip_svc_std,
Hadi Asyrafi616da772019-06-27 11:34:03 +0800373 OEN_SIP_START,
374 OEN_SIP_END,
375 SMC_TYPE_YIELD,
376 NULL,
377 sip_smc_handler
378);