Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2018 Marvell International Ltd. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * https://spdx.org/licenses |
| 6 | */ |
| 7 | |
Konstantin Porotchkin | 91db290 | 2018-07-29 13:30:51 +0300 | [diff] [blame] | 8 | #include <armada_common.h> |
Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 9 | #include <assert.h> |
| 10 | #include <bakery_lock.h> |
| 11 | #include <debug.h> |
| 12 | #include <delay_timer.h> |
| 13 | #include <cache_llc.h> |
| 14 | #include <console.h> |
| 15 | #include <gicv2.h> |
| 16 | #include <marvell_pm.h> |
| 17 | #include <mmio.h> |
| 18 | #include <mss_pm_ipc.h> |
| 19 | #include <plat_marvell.h> |
| 20 | #include <platform.h> |
| 21 | #include <plat_pm_trace.h> |
| 22 | #include <platform.h> |
| 23 | |
| 24 | #define MVEBU_PRIVATE_UID_REG 0x30 |
| 25 | #define MVEBU_RFU_GLOBL_SW_RST 0x84 |
| 26 | #define MVEBU_CCU_RVBAR(cpu) (MVEBU_REGS_BASE + 0x640 + (cpu * 4)) |
| 27 | #define MVEBU_CCU_CPU_UN_RESET(cpu) (MVEBU_REGS_BASE + 0x650 + (cpu * 4)) |
| 28 | |
| 29 | #define MPIDR_CPU_GET(mpidr) ((mpidr) & MPIDR_CPU_MASK) |
| 30 | #define MPIDR_CLUSTER_GET(mpidr) MPIDR_AFFLVL1_VAL((mpidr)) |
| 31 | |
| 32 | #define MVEBU_GPIO_MASK(index) (1 << (index % 32)) |
| 33 | #define MVEBU_MPP_MASK(index) (0xF << (4 * (index % 8))) |
| 34 | #define MVEBU_GPIO_VALUE(index, value) (value << (index % 32)) |
| 35 | |
| 36 | #define MVEBU_USER_CMD_0_REG (MVEBU_DRAM_MAC_BASE + 0x20) |
| 37 | #define MVEBU_USER_CMD_CH0_OFFSET 28 |
| 38 | #define MVEBU_USER_CMD_CH0_MASK (1 << MVEBU_USER_CMD_CH0_OFFSET) |
| 39 | #define MVEBU_USER_CMD_CH0_EN (1 << MVEBU_USER_CMD_CH0_OFFSET) |
| 40 | #define MVEBU_USER_CMD_CS_OFFSET 24 |
| 41 | #define MVEBU_USER_CMD_CS_MASK (0xF << MVEBU_USER_CMD_CS_OFFSET) |
| 42 | #define MVEBU_USER_CMD_CS_ALL (0xF << MVEBU_USER_CMD_CS_OFFSET) |
| 43 | #define MVEBU_USER_CMD_SR_OFFSET 6 |
| 44 | #define MVEBU_USER_CMD_SR_MASK (0x3 << MVEBU_USER_CMD_SR_OFFSET) |
| 45 | #define MVEBU_USER_CMD_SR_ENTER (0x1 << MVEBU_USER_CMD_SR_OFFSET) |
| 46 | #define MVEBU_MC_PWR_CTRL_REG (MVEBU_DRAM_MAC_BASE + 0x54) |
| 47 | #define MVEBU_MC_AC_ON_DLY_OFFSET 8 |
| 48 | #define MVEBU_MC_AC_ON_DLY_MASK (0xF << MVEBU_MC_AC_ON_DLY_OFFSET) |
| 49 | #define MVEBU_MC_AC_ON_DLY_DEF_VAR (8 << MVEBU_MC_AC_ON_DLY_OFFSET) |
| 50 | #define MVEBU_MC_AC_OFF_DLY_OFFSET 4 |
| 51 | #define MVEBU_MC_AC_OFF_DLY_MASK (0xF << MVEBU_MC_AC_OFF_DLY_OFFSET) |
| 52 | #define MVEBU_MC_AC_OFF_DLY_DEF_VAR (0xC << MVEBU_MC_AC_OFF_DLY_OFFSET) |
| 53 | #define MVEBU_MC_PHY_AUTO_OFF_OFFSET 0 |
| 54 | #define MVEBU_MC_PHY_AUTO_OFF_MASK (1 << MVEBU_MC_PHY_AUTO_OFF_OFFSET) |
| 55 | #define MVEBU_MC_PHY_AUTO_OFF_EN (1 << MVEBU_MC_PHY_AUTO_OFF_OFFSET) |
| 56 | |
| 57 | /* this lock synchronize AP multiple cores execution with MSS */ |
| 58 | DEFINE_BAKERY_LOCK(pm_sys_lock); |
| 59 | |
| 60 | /* Weak definitions may be overridden in specific board */ |
| 61 | #pragma weak plat_marvell_get_pm_cfg |
| 62 | |
| 63 | /* AP806 CPU power down /power up definitions */ |
| 64 | enum CPU_ID { |
| 65 | CPU0, |
| 66 | CPU1, |
| 67 | CPU2, |
| 68 | CPU3 |
| 69 | }; |
| 70 | |
| 71 | #define REG_WR_VALIDATE_TIMEOUT (2000) |
| 72 | |
| 73 | #define FEATURE_DISABLE_STATUS_REG \ |
| 74 | (MVEBU_REGS_BASE + 0x6F8230) |
| 75 | #define FEATURE_DISABLE_STATUS_CPU_CLUSTER_OFFSET 4 |
| 76 | #define FEATURE_DISABLE_STATUS_CPU_CLUSTER_MASK \ |
| 77 | (0x1 << FEATURE_DISABLE_STATUS_CPU_CLUSTER_OFFSET) |
| 78 | |
| 79 | #ifdef MVEBU_SOC_AP807 |
| 80 | #define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET 1 |
| 81 | #define PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET 0 |
| 82 | #else |
| 83 | #define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET 0 |
| 84 | #define PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET 31 |
| 85 | #endif |
| 86 | |
| 87 | #define PWRC_CPUN_CR_REG(cpu_id) \ |
| 88 | (MVEBU_REGS_BASE + 0x680000 + (cpu_id * 0x10)) |
| 89 | #define PWRC_CPUN_CR_PWR_DN_RQ_MASK \ |
| 90 | (0x1 << PWRC_CPUN_CR_PWR_DN_RQ_OFFSET) |
| 91 | #define PWRC_CPUN_CR_ISO_ENABLE_OFFSET 16 |
| 92 | #define PWRC_CPUN_CR_ISO_ENABLE_MASK \ |
| 93 | (0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET) |
| 94 | #define PWRC_CPUN_CR_LDO_BYPASS_RDY_MASK \ |
| 95 | (0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET) |
| 96 | |
| 97 | #define CCU_B_PRCRN_REG(cpu_id) \ |
| 98 | (MVEBU_REGS_BASE + 0x1A50 + \ |
| 99 | ((cpu_id / 2) * (0x400)) + ((cpu_id % 2) * 4)) |
| 100 | #define CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET 0 |
| 101 | #define CCU_B_PRCRN_CPUPORESET_STATIC_MASK \ |
| 102 | (0x1 << CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET) |
| 103 | |
| 104 | /* power switch fingers */ |
| 105 | #define AP807_PWRC_LDO_CR0_REG \ |
| 106 | (MVEBU_REGS_BASE + 0x680000 + 0x100) |
| 107 | #define AP807_PWRC_LDO_CR0_OFFSET 16 |
| 108 | #define AP807_PWRC_LDO_CR0_MASK \ |
| 109 | (0xff << AP807_PWRC_LDO_CR0_OFFSET) |
| 110 | #define AP807_PWRC_LDO_CR0_VAL 0xfd |
| 111 | |
| 112 | /* |
| 113 | * Power down CPU: |
| 114 | * Used to reduce power consumption, and avoid SoC unnecessary temperature rise. |
| 115 | */ |
| 116 | static int plat_marvell_cpu_powerdown(int cpu_id) |
| 117 | { |
| 118 | uint32_t reg_val; |
| 119 | int exit_loop = REG_WR_VALIDATE_TIMEOUT; |
| 120 | |
| 121 | INFO("Powering down CPU%d\n", cpu_id); |
| 122 | |
| 123 | /* 1. Isolation enable */ |
| 124 | reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); |
| 125 | reg_val |= 0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET; |
| 126 | mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); |
| 127 | |
| 128 | /* 2. Read and check Isolation enabled - verify bit set to 1 */ |
| 129 | do { |
| 130 | reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); |
| 131 | exit_loop--; |
| 132 | } while (!(reg_val & (0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET)) && |
| 133 | exit_loop > 0); |
| 134 | |
| 135 | /* 3. Switch off CPU power */ |
| 136 | reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); |
| 137 | reg_val &= ~PWRC_CPUN_CR_PWR_DN_RQ_MASK; |
| 138 | mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); |
| 139 | |
| 140 | /* 4. Read and check Switch Off - verify bit set to 0 */ |
| 141 | exit_loop = REG_WR_VALIDATE_TIMEOUT; |
| 142 | do { |
| 143 | reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); |
| 144 | exit_loop--; |
| 145 | } while (reg_val & PWRC_CPUN_CR_PWR_DN_RQ_MASK && exit_loop > 0); |
| 146 | |
| 147 | if (exit_loop <= 0) |
| 148 | goto cpu_poweroff_error; |
| 149 | |
| 150 | /* 5. De-Assert power ready */ |
| 151 | reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); |
| 152 | reg_val &= ~PWRC_CPUN_CR_LDO_BYPASS_RDY_MASK; |
| 153 | mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); |
| 154 | |
| 155 | /* 6. Assert CPU POR reset */ |
| 156 | reg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id)); |
| 157 | reg_val &= ~CCU_B_PRCRN_CPUPORESET_STATIC_MASK; |
| 158 | mmio_write_32(CCU_B_PRCRN_REG(cpu_id), reg_val); |
| 159 | |
| 160 | /* 7. Read and poll on Validate the CPU is out of reset */ |
| 161 | exit_loop = REG_WR_VALIDATE_TIMEOUT; |
| 162 | do { |
| 163 | reg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id)); |
| 164 | exit_loop--; |
| 165 | } while (reg_val & CCU_B_PRCRN_CPUPORESET_STATIC_MASK && exit_loop > 0); |
| 166 | |
| 167 | if (exit_loop <= 0) |
| 168 | goto cpu_poweroff_error; |
| 169 | |
| 170 | INFO("Successfully powered down CPU%d\n", cpu_id); |
| 171 | |
| 172 | return 0; |
| 173 | |
| 174 | cpu_poweroff_error: |
| 175 | ERROR("ERROR: Can't power down CPU%d\n", cpu_id); |
| 176 | return -1; |
| 177 | } |
| 178 | |
| 179 | /* |
| 180 | * Power down CPUs 1-3 at early boot stage, |
| 181 | * to reduce power consumption and SoC temperature. |
| 182 | * This is triggered by BLE prior to DDR initialization. |
| 183 | * |
| 184 | * Note: |
| 185 | * All CPUs will be powered up by plat_marvell_cpu_powerup on Linux boot stage, |
| 186 | * which is triggered by PSCI ops (pwr_domain_on). |
| 187 | */ |
| 188 | int plat_marvell_early_cpu_powerdown(void) |
| 189 | { |
| 190 | uint32_t cpu_cluster_status = |
| 191 | mmio_read_32(FEATURE_DISABLE_STATUS_REG) & |
| 192 | FEATURE_DISABLE_STATUS_CPU_CLUSTER_MASK; |
| 193 | /* if cpu_cluster_status bit is set, |
| 194 | * that means we have only single cluster |
| 195 | */ |
| 196 | int cluster_count = cpu_cluster_status ? 1 : 2; |
| 197 | |
| 198 | INFO("Powering off unused CPUs\n"); |
| 199 | |
| 200 | /* CPU1 is in AP806 cluster-0, which always exists, so power it down */ |
| 201 | if (plat_marvell_cpu_powerdown(CPU1) == -1) |
| 202 | return -1; |
| 203 | |
| 204 | /* |
| 205 | * CPU2-3 are in AP806 2nd cluster (cluster-1), |
| 206 | * which doesn't exists in dual-core systems. |
| 207 | * so need to check if we have dual-core (single cluster) |
| 208 | * or quad-code (2 clusters) |
| 209 | */ |
| 210 | if (cluster_count == 2) { |
| 211 | /* CPU2-3 are part of 2nd cluster */ |
| 212 | if (plat_marvell_cpu_powerdown(CPU2) == -1) |
| 213 | return -1; |
| 214 | if (plat_marvell_cpu_powerdown(CPU3) == -1) |
| 215 | return -1; |
| 216 | } |
| 217 | |
| 218 | return 0; |
| 219 | } |
| 220 | |
| 221 | /* |
| 222 | * Power up CPU - part of Linux boot stage |
| 223 | */ |
| 224 | static int plat_marvell_cpu_powerup(u_register_t mpidr) |
| 225 | { |
| 226 | uint32_t reg_val; |
| 227 | int cpu_id = MPIDR_CPU_GET(mpidr), |
| 228 | cluster = MPIDR_CLUSTER_GET(mpidr); |
| 229 | int exit_loop = REG_WR_VALIDATE_TIMEOUT; |
| 230 | |
| 231 | /* calculate absolute CPU ID */ |
| 232 | cpu_id = cluster * PLAT_MARVELL_CLUSTER_CORE_COUNT + cpu_id; |
| 233 | |
| 234 | INFO("Powering on CPU%d\n", cpu_id); |
| 235 | |
| 236 | #ifdef MVEBU_SOC_AP807 |
| 237 | /* Activate 2 power switch fingers */ |
| 238 | reg_val = mmio_read_32(AP807_PWRC_LDO_CR0_REG); |
| 239 | reg_val &= ~(AP807_PWRC_LDO_CR0_MASK); |
| 240 | reg_val |= (AP807_PWRC_LDO_CR0_VAL << AP807_PWRC_LDO_CR0_OFFSET); |
| 241 | mmio_write_32(AP807_PWRC_LDO_CR0_REG, reg_val); |
| 242 | udelay(100); |
| 243 | #endif |
| 244 | |
| 245 | /* 1. Switch CPU power ON */ |
| 246 | reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); |
| 247 | reg_val |= 0x1 << PWRC_CPUN_CR_PWR_DN_RQ_OFFSET; |
| 248 | mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); |
| 249 | |
| 250 | /* 2. Wait for CPU on, up to 100 uSec: */ |
| 251 | udelay(100); |
| 252 | |
| 253 | /* 3. Assert power ready */ |
| 254 | reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); |
| 255 | reg_val |= 0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET; |
| 256 | mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); |
| 257 | |
| 258 | /* 4. Read & Validate power ready |
| 259 | * used in order to generate 16 Host CPU cycles |
| 260 | */ |
| 261 | do { |
| 262 | reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); |
| 263 | exit_loop--; |
| 264 | } while (!(reg_val & (0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET)) && |
| 265 | exit_loop > 0); |
| 266 | |
| 267 | if (exit_loop <= 0) |
| 268 | goto cpu_poweron_error; |
| 269 | |
| 270 | /* 5. Isolation disable */ |
| 271 | reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); |
| 272 | reg_val &= ~PWRC_CPUN_CR_ISO_ENABLE_MASK; |
| 273 | mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); |
| 274 | |
| 275 | /* 6. Read and check Isolation enabled - verify bit set to 1 */ |
| 276 | exit_loop = REG_WR_VALIDATE_TIMEOUT; |
| 277 | do { |
| 278 | reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); |
| 279 | exit_loop--; |
| 280 | } while ((reg_val & (0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET)) && |
| 281 | exit_loop > 0); |
| 282 | |
| 283 | /* 7. De Assert CPU POR reset & Core reset */ |
| 284 | reg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id)); |
| 285 | reg_val |= 0x1 << CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET; |
| 286 | mmio_write_32(CCU_B_PRCRN_REG(cpu_id), reg_val); |
| 287 | |
| 288 | /* 8. Read & Validate CPU POR reset */ |
| 289 | exit_loop = REG_WR_VALIDATE_TIMEOUT; |
| 290 | do { |
| 291 | reg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id)); |
| 292 | exit_loop--; |
| 293 | } while (!(reg_val & (0x1 << CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET)) && |
| 294 | exit_loop > 0); |
| 295 | |
| 296 | if (exit_loop <= 0) |
| 297 | goto cpu_poweron_error; |
| 298 | |
| 299 | INFO("Successfully powered on CPU%d\n", cpu_id); |
| 300 | |
| 301 | return 0; |
| 302 | |
| 303 | cpu_poweron_error: |
| 304 | ERROR("ERROR: Can't power up CPU%d\n", cpu_id); |
| 305 | return -1; |
| 306 | } |
| 307 | |
| 308 | static int plat_marvell_cpu_on(u_register_t mpidr) |
| 309 | { |
| 310 | int cpu_id; |
| 311 | int cluster; |
| 312 | |
| 313 | /* Set barierr */ |
| 314 | dsbsy(); |
| 315 | |
| 316 | /* Get cpu number - use CPU ID */ |
| 317 | cpu_id = MPIDR_CPU_GET(mpidr); |
| 318 | |
| 319 | /* Get cluster number - use affinity level 1 */ |
| 320 | cluster = MPIDR_CLUSTER_GET(mpidr); |
| 321 | |
| 322 | /* Set CPU private UID */ |
| 323 | mmio_write_32(MVEBU_REGS_BASE + MVEBU_PRIVATE_UID_REG, cluster + 0x4); |
| 324 | |
| 325 | /* Set the cpu start address to BL1 entry point (align to 0x10000) */ |
| 326 | mmio_write_32(MVEBU_CCU_RVBAR(cpu_id), |
| 327 | PLAT_MARVELL_CPU_ENTRY_ADDR >> 16); |
| 328 | |
| 329 | /* Get the cpu out of reset */ |
| 330 | mmio_write_32(MVEBU_CCU_CPU_UN_RESET(cpu_id), 0x10001); |
| 331 | |
| 332 | return 0; |
| 333 | } |
| 334 | |
| 335 | /***************************************************************************** |
| 336 | * A8K handler called to check the validity of the power state |
| 337 | * parameter. |
| 338 | ***************************************************************************** |
| 339 | */ |
| 340 | static int a8k_validate_power_state(unsigned int power_state, |
| 341 | psci_power_state_t *req_state) |
| 342 | { |
| 343 | int pstate = psci_get_pstate_type(power_state); |
| 344 | int pwr_lvl = psci_get_pstate_pwrlvl(power_state); |
| 345 | int i; |
| 346 | |
| 347 | if (pwr_lvl > PLAT_MAX_PWR_LVL) |
| 348 | return PSCI_E_INVALID_PARAMS; |
| 349 | |
| 350 | /* Sanity check the requested state */ |
| 351 | if (pstate == PSTATE_TYPE_STANDBY) { |
| 352 | /* |
| 353 | * It's possible to enter standby only on power level 0 |
| 354 | * Ignore any other power level. |
| 355 | */ |
| 356 | if (pwr_lvl != MARVELL_PWR_LVL0) |
| 357 | return PSCI_E_INVALID_PARAMS; |
| 358 | |
| 359 | req_state->pwr_domain_state[MARVELL_PWR_LVL0] = |
| 360 | MARVELL_LOCAL_STATE_RET; |
| 361 | } else { |
| 362 | for (i = MARVELL_PWR_LVL0; i <= pwr_lvl; i++) |
| 363 | req_state->pwr_domain_state[i] = |
| 364 | MARVELL_LOCAL_STATE_OFF; |
| 365 | } |
| 366 | |
| 367 | /* |
| 368 | * We expect the 'state id' to be zero. |
| 369 | */ |
| 370 | if (psci_get_pstate_id(power_state)) |
| 371 | return PSCI_E_INVALID_PARAMS; |
| 372 | |
| 373 | return PSCI_E_SUCCESS; |
| 374 | } |
| 375 | |
| 376 | /***************************************************************************** |
| 377 | * A8K handler called when a CPU is about to enter standby. |
| 378 | ***************************************************************************** |
| 379 | */ |
| 380 | static void a8k_cpu_standby(plat_local_state_t cpu_state) |
| 381 | { |
Marcin Wojtas | 46b6535 | 2017-11-16 18:19:02 +0100 | [diff] [blame^] | 382 | if (!is_pm_fw_running()) { |
| 383 | ERROR("%s: needs to be implemented\n", __func__); |
| 384 | panic(); |
| 385 | } |
Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 386 | } |
| 387 | |
| 388 | /***************************************************************************** |
| 389 | * A8K handler called when a power domain is about to be turned on. The |
| 390 | * mpidr determines the CPU to be turned on. |
| 391 | ***************************************************************************** |
| 392 | */ |
| 393 | static int a8k_pwr_domain_on(u_register_t mpidr) |
| 394 | { |
| 395 | /* Power up CPU (CPUs 1-3 are powered off at start of BLE) */ |
| 396 | plat_marvell_cpu_powerup(mpidr); |
| 397 | |
| 398 | if (is_pm_fw_running()) { |
| 399 | unsigned int target = |
| 400 | ((mpidr & 0xFF) + (((mpidr >> 8) & 0xFF) * 2)); |
| 401 | |
| 402 | /* |
| 403 | * pm system synchronization - used to synchronize |
| 404 | * multiple core access to MSS |
| 405 | */ |
| 406 | bakery_lock_get(&pm_sys_lock); |
| 407 | |
| 408 | /* send CPU ON IPC Message to MSS */ |
| 409 | mss_pm_ipc_msg_send(target, PM_IPC_MSG_CPU_ON, 0); |
| 410 | |
| 411 | /* trigger IPC message to MSS */ |
| 412 | mss_pm_ipc_msg_trigger(); |
| 413 | |
| 414 | /* pm system synchronization */ |
| 415 | bakery_lock_release(&pm_sys_lock); |
| 416 | |
| 417 | /* trace message */ |
| 418 | PM_TRACE(TRACE_PWR_DOMAIN_ON | target); |
| 419 | } else { |
| 420 | /* proprietary CPU ON exection flow */ |
| 421 | plat_marvell_cpu_on(mpidr); |
| 422 | } |
| 423 | |
| 424 | return 0; |
| 425 | } |
| 426 | |
| 427 | /***************************************************************************** |
| 428 | * A8K handler called to validate the entry point. |
| 429 | ***************************************************************************** |
| 430 | */ |
| 431 | static int a8k_validate_ns_entrypoint(uintptr_t entrypoint) |
| 432 | { |
| 433 | return PSCI_E_SUCCESS; |
| 434 | } |
| 435 | |
| 436 | /***************************************************************************** |
| 437 | * A8K handler called when a power domain is about to be turned off. The |
| 438 | * target_state encodes the power state that each level should transition to. |
| 439 | ***************************************************************************** |
| 440 | */ |
| 441 | static void a8k_pwr_domain_off(const psci_power_state_t *target_state) |
| 442 | { |
| 443 | if (is_pm_fw_running()) { |
| 444 | unsigned int idx = plat_my_core_pos(); |
| 445 | |
| 446 | /* Prevent interrupts from spuriously waking up this cpu */ |
| 447 | gicv2_cpuif_disable(); |
| 448 | |
| 449 | /* pm system synchronization - used to synchronize multiple |
| 450 | * core access to MSS |
| 451 | */ |
| 452 | bakery_lock_get(&pm_sys_lock); |
| 453 | |
| 454 | /* send CPU OFF IPC Message to MSS */ |
| 455 | mss_pm_ipc_msg_send(idx, PM_IPC_MSG_CPU_OFF, target_state); |
| 456 | |
| 457 | /* trigger IPC message to MSS */ |
| 458 | mss_pm_ipc_msg_trigger(); |
| 459 | |
| 460 | /* pm system synchronization */ |
| 461 | bakery_lock_release(&pm_sys_lock); |
| 462 | |
| 463 | /* trace message */ |
| 464 | PM_TRACE(TRACE_PWR_DOMAIN_OFF); |
| 465 | } else { |
| 466 | INFO("%s: is not supported without SCP\n", __func__); |
| 467 | } |
| 468 | } |
| 469 | |
| 470 | /* Get PM config to power off the SoC */ |
| 471 | void *plat_marvell_get_pm_cfg(void) |
| 472 | { |
| 473 | return NULL; |
| 474 | } |
| 475 | |
| 476 | /* |
| 477 | * This function should be called on restore from |
| 478 | * "suspend to RAM" state when the execution flow |
| 479 | * has to bypass BootROM image to RAM copy and speed up |
| 480 | * the system recovery |
| 481 | * |
| 482 | */ |
| 483 | static void plat_marvell_exit_bootrom(void) |
| 484 | { |
| 485 | marvell_exit_bootrom(PLAT_MARVELL_TRUSTED_ROM_BASE); |
| 486 | } |
| 487 | |
| 488 | /* |
| 489 | * Prepare for the power off of the system via GPIO |
| 490 | */ |
| 491 | static void plat_marvell_power_off_gpio(struct power_off_method *pm_cfg, |
| 492 | register_t *gpio_addr, |
| 493 | register_t *gpio_data) |
| 494 | { |
| 495 | unsigned int gpio; |
| 496 | unsigned int idx; |
| 497 | unsigned int shift; |
| 498 | unsigned int reg; |
| 499 | unsigned int addr; |
| 500 | gpio_info_t *info; |
| 501 | unsigned int tog_bits; |
| 502 | |
| 503 | assert((pm_cfg->cfg.gpio.pin_count < PMIC_GPIO_MAX_NUMBER) && |
| 504 | (pm_cfg->cfg.gpio.step_count < PMIC_GPIO_MAX_TOGGLE_STEP)); |
| 505 | |
| 506 | /* Prepare GPIOs for PMIC */ |
| 507 | for (gpio = 0; gpio < pm_cfg->cfg.gpio.pin_count; gpio++) { |
| 508 | info = &pm_cfg->cfg.gpio.info[gpio]; |
| 509 | /* Set PMIC GPIO to output mode */ |
| 510 | reg = mmio_read_32(MVEBU_CP_GPIO_DATA_OUT_EN( |
| 511 | info->cp_index, info->gpio_index)); |
| 512 | mmio_write_32(MVEBU_CP_GPIO_DATA_OUT_EN( |
| 513 | info->cp_index, info->gpio_index), |
| 514 | reg & ~MVEBU_GPIO_MASK(info->gpio_index)); |
| 515 | |
| 516 | /* Set the appropriate MPP to GPIO mode */ |
| 517 | reg = mmio_read_32(MVEBU_PM_MPP_REGS(info->cp_index, |
| 518 | info->gpio_index)); |
| 519 | mmio_write_32(MVEBU_PM_MPP_REGS(info->cp_index, |
| 520 | info->gpio_index), |
| 521 | reg & ~MVEBU_MPP_MASK(info->gpio_index)); |
| 522 | } |
| 523 | |
| 524 | /* Wait for MPP & GPIO pre-configurations done */ |
| 525 | mdelay(pm_cfg->cfg.gpio.delay_ms); |
| 526 | |
| 527 | /* Toggle the GPIO values, and leave final step to be triggered |
| 528 | * after DDR self-refresh is enabled |
| 529 | */ |
| 530 | for (idx = 0; idx < pm_cfg->cfg.gpio.step_count; idx++) { |
| 531 | tog_bits = pm_cfg->cfg.gpio.seq[idx]; |
| 532 | |
| 533 | /* The GPIOs must be within same GPIO register, |
| 534 | * thus could get the original value by first GPIO |
| 535 | */ |
| 536 | info = &pm_cfg->cfg.gpio.info[0]; |
| 537 | reg = mmio_read_32(MVEBU_CP_GPIO_DATA_OUT( |
| 538 | info->cp_index, info->gpio_index)); |
| 539 | addr = MVEBU_CP_GPIO_DATA_OUT(info->cp_index, info->gpio_index); |
| 540 | |
| 541 | for (gpio = 0; gpio < pm_cfg->cfg.gpio.pin_count; gpio++) { |
| 542 | shift = pm_cfg->cfg.gpio.info[gpio].gpio_index % 32; |
| 543 | if (GPIO_LOW == (tog_bits & (1 << gpio))) |
| 544 | reg &= ~(1 << shift); |
| 545 | else |
| 546 | reg |= (1 << shift); |
| 547 | } |
| 548 | |
| 549 | /* Set the GPIO register, for last step just store |
| 550 | * register address and values to system registers |
| 551 | */ |
| 552 | if (idx < pm_cfg->cfg.gpio.step_count - 1) { |
| 553 | mmio_write_32(MVEBU_CP_GPIO_DATA_OUT( |
| 554 | info->cp_index, info->gpio_index), reg); |
| 555 | mdelay(pm_cfg->cfg.gpio.delay_ms); |
| 556 | } else { |
| 557 | /* Save GPIO register and address values for |
| 558 | * finishing the power down operation later |
| 559 | */ |
| 560 | *gpio_addr = addr; |
| 561 | *gpio_data = reg; |
| 562 | } |
| 563 | } |
| 564 | } |
| 565 | |
| 566 | /* |
| 567 | * Prepare for the power off of the system |
| 568 | */ |
| 569 | static void plat_marvell_power_off_prepare(struct power_off_method *pm_cfg, |
| 570 | register_t *addr, register_t *data) |
| 571 | { |
| 572 | switch (pm_cfg->type) { |
| 573 | case PMIC_GPIO: |
| 574 | plat_marvell_power_off_gpio(pm_cfg, addr, data); |
| 575 | break; |
| 576 | default: |
| 577 | break; |
| 578 | } |
| 579 | } |
| 580 | |
| 581 | /***************************************************************************** |
| 582 | * A8K handler called when a power domain is about to be suspended. The |
| 583 | * target_state encodes the power state that each level should transition to. |
| 584 | ***************************************************************************** |
| 585 | */ |
| 586 | static void a8k_pwr_domain_suspend(const psci_power_state_t *target_state) |
| 587 | { |
| 588 | if (is_pm_fw_running()) { |
| 589 | unsigned int idx; |
| 590 | |
| 591 | /* Prevent interrupts from spuriously waking up this cpu */ |
| 592 | gicv2_cpuif_disable(); |
| 593 | |
| 594 | idx = plat_my_core_pos(); |
| 595 | |
| 596 | /* pm system synchronization - used to synchronize multiple |
| 597 | * core access to MSS |
| 598 | */ |
| 599 | bakery_lock_get(&pm_sys_lock); |
| 600 | |
| 601 | /* send CPU Suspend IPC Message to MSS */ |
| 602 | mss_pm_ipc_msg_send(idx, PM_IPC_MSG_CPU_SUSPEND, target_state); |
| 603 | |
| 604 | /* trigger IPC message to MSS */ |
| 605 | mss_pm_ipc_msg_trigger(); |
| 606 | |
| 607 | /* pm system synchronization */ |
| 608 | bakery_lock_release(&pm_sys_lock); |
| 609 | |
| 610 | /* trace message */ |
| 611 | PM_TRACE(TRACE_PWR_DOMAIN_SUSPEND); |
| 612 | } else { |
| 613 | uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; |
| 614 | |
| 615 | INFO("Suspending to RAM\n"); |
| 616 | |
| 617 | /* Prevent interrupts from spuriously waking up this cpu */ |
| 618 | gicv2_cpuif_disable(); |
| 619 | |
| 620 | mailbox[MBOX_IDX_SUSPEND_MAGIC] = MVEBU_MAILBOX_SUSPEND_STATE; |
| 621 | mailbox[MBOX_IDX_ROM_EXIT_ADDR] = (uintptr_t)&plat_marvell_exit_bootrom; |
| 622 | |
| 623 | #if PLAT_MARVELL_SHARED_RAM_CACHED |
| 624 | flush_dcache_range(PLAT_MARVELL_MAILBOX_BASE + |
| 625 | MBOX_IDX_SUSPEND_MAGIC * sizeof(uintptr_t), |
| 626 | 2 * sizeof(uintptr_t)); |
| 627 | #endif |
| 628 | /* Flush and disable LLC before going off-power */ |
| 629 | llc_disable(0); |
| 630 | |
| 631 | isb(); |
| 632 | /* |
| 633 | * Do not halt here! |
| 634 | * The function must return for allowing the caller function |
| 635 | * psci_power_up_finish() to do the proper context saving and |
| 636 | * to release the CPU lock. |
| 637 | */ |
| 638 | } |
| 639 | } |
| 640 | |
| 641 | /***************************************************************************** |
| 642 | * A8K handler called when a power domain has just been powered on after |
| 643 | * being turned off earlier. The target_state encodes the low power state that |
| 644 | * each level has woken up from. |
| 645 | ***************************************************************************** |
| 646 | */ |
| 647 | static void a8k_pwr_domain_on_finish(const psci_power_state_t *target_state) |
| 648 | { |
| 649 | /* arch specific configuration */ |
| 650 | marvell_psci_arch_init(0); |
| 651 | |
| 652 | /* Interrupt initialization */ |
| 653 | gicv2_pcpu_distif_init(); |
| 654 | gicv2_cpuif_enable(); |
| 655 | |
| 656 | if (is_pm_fw_running()) { |
| 657 | /* trace message */ |
| 658 | PM_TRACE(TRACE_PWR_DOMAIN_ON_FINISH); |
| 659 | } |
| 660 | } |
| 661 | |
| 662 | /***************************************************************************** |
| 663 | * A8K handler called when a power domain has just been powered on after |
| 664 | * having been suspended earlier. The target_state encodes the low power state |
| 665 | * that each level has woken up from. |
| 666 | * TODO: At the moment we reuse the on finisher and reinitialize the secure |
| 667 | * context. Need to implement a separate suspend finisher. |
| 668 | ***************************************************************************** |
| 669 | */ |
| 670 | static void a8k_pwr_domain_suspend_finish( |
| 671 | const psci_power_state_t *target_state) |
| 672 | { |
| 673 | if (is_pm_fw_running()) { |
| 674 | /* arch specific configuration */ |
| 675 | marvell_psci_arch_init(0); |
| 676 | |
| 677 | /* Interrupt initialization */ |
| 678 | gicv2_cpuif_enable(); |
| 679 | |
| 680 | /* trace message */ |
| 681 | PM_TRACE(TRACE_PWR_DOMAIN_SUSPEND_FINISH); |
| 682 | } else { |
| 683 | uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; |
| 684 | |
| 685 | /* Only primary CPU requres platform init */ |
| 686 | if (!plat_my_core_pos()) { |
| 687 | /* Initialize the console to provide |
| 688 | * early debug support |
| 689 | */ |
| 690 | console_init(PLAT_MARVELL_BOOT_UART_BASE, |
| 691 | PLAT_MARVELL_BOOT_UART_CLK_IN_HZ, |
| 692 | MARVELL_CONSOLE_BAUDRATE); |
| 693 | |
| 694 | bl31_plat_arch_setup(); |
| 695 | marvell_bl31_platform_setup(); |
| 696 | /* |
| 697 | * Remove suspend to RAM marker from the mailbox |
| 698 | * for treating a regular reset as a cold boot |
| 699 | */ |
| 700 | mailbox[MBOX_IDX_SUSPEND_MAGIC] = 0; |
| 701 | mailbox[MBOX_IDX_ROM_EXIT_ADDR] = 0; |
| 702 | #if PLAT_MARVELL_SHARED_RAM_CACHED |
| 703 | flush_dcache_range(PLAT_MARVELL_MAILBOX_BASE + |
| 704 | MBOX_IDX_SUSPEND_MAGIC * sizeof(uintptr_t), |
| 705 | 2 * sizeof(uintptr_t)); |
| 706 | #endif |
| 707 | } |
| 708 | } |
| 709 | } |
| 710 | |
| 711 | /***************************************************************************** |
| 712 | * This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND` |
| 713 | * call to get the `power_state` parameter. This allows the platform to encode |
| 714 | * the appropriate State-ID field within the `power_state` parameter which can |
| 715 | * be utilized in `pwr_domain_suspend()` to suspend to system affinity level. |
| 716 | ***************************************************************************** |
| 717 | */ |
| 718 | static void a8k_get_sys_suspend_power_state(psci_power_state_t *req_state) |
| 719 | { |
| 720 | /* lower affinities use PLAT_MAX_OFF_STATE */ |
| 721 | for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) |
| 722 | req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; |
| 723 | } |
| 724 | |
| 725 | static void |
| 726 | __dead2 a8k_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) |
| 727 | { |
| 728 | struct power_off_method *pm_cfg; |
| 729 | unsigned int srcmd; |
| 730 | unsigned int sdram_reg; |
| 731 | register_t gpio_data = 0, gpio_addr = 0; |
| 732 | |
| 733 | if (is_pm_fw_running()) { |
| 734 | psci_power_down_wfi(); |
| 735 | panic(); |
| 736 | } |
| 737 | |
| 738 | pm_cfg = (struct power_off_method *)plat_marvell_get_pm_cfg(); |
| 739 | |
| 740 | /* Prepare for power off */ |
| 741 | plat_marvell_power_off_prepare(pm_cfg, &gpio_addr, &gpio_data); |
| 742 | |
| 743 | /* First step to enable DDR self-refresh |
| 744 | * to keep the data during suspend |
| 745 | */ |
| 746 | mmio_write_32(MVEBU_MC_PWR_CTRL_REG, 0x8C1); |
| 747 | |
| 748 | /* Save DDR self-refresh second step register |
| 749 | * and value to be issued later |
| 750 | */ |
| 751 | sdram_reg = MVEBU_USER_CMD_0_REG; |
| 752 | srcmd = mmio_read_32(sdram_reg); |
| 753 | srcmd &= ~(MVEBU_USER_CMD_CH0_MASK | MVEBU_USER_CMD_CS_MASK | |
| 754 | MVEBU_USER_CMD_SR_MASK); |
| 755 | srcmd |= (MVEBU_USER_CMD_CH0_EN | MVEBU_USER_CMD_CS_ALL | |
| 756 | MVEBU_USER_CMD_SR_ENTER); |
| 757 | |
| 758 | /* |
| 759 | * Wait for DRAM is done using registers access only. |
| 760 | * At this stage any access to DRAM (procedure call) will |
| 761 | * release it from the self-refresh mode |
| 762 | */ |
| 763 | __asm__ volatile ( |
| 764 | /* Align to a cache line */ |
| 765 | " .balign 64\n\t" |
| 766 | |
| 767 | /* Enter self refresh */ |
| 768 | " str %[srcmd], [%[sdram_reg]]\n\t" |
| 769 | |
| 770 | /* |
| 771 | * Wait 100 cycles for DDR to enter self refresh, by |
| 772 | * doing 50 times two instructions. |
| 773 | */ |
| 774 | " mov x1, #50\n\t" |
| 775 | "1: subs x1, x1, #1\n\t" |
| 776 | " bne 1b\n\t" |
| 777 | |
| 778 | /* Issue the command to trigger the SoC power off */ |
| 779 | " str %[gpio_data], [%[gpio_addr]]\n\t" |
| 780 | |
| 781 | /* Trap the processor */ |
| 782 | " b .\n\t" |
| 783 | : : [srcmd] "r" (srcmd), [sdram_reg] "r" (sdram_reg), |
| 784 | [gpio_addr] "r" (gpio_addr), [gpio_data] "r" (gpio_data) |
| 785 | : "x1"); |
| 786 | |
| 787 | panic(); |
| 788 | } |
| 789 | |
| 790 | /***************************************************************************** |
| 791 | * A8K handlers to shutdown/reboot the system |
| 792 | ***************************************************************************** |
| 793 | */ |
| 794 | static void __dead2 a8k_system_off(void) |
| 795 | { |
| 796 | ERROR("%s: needs to be implemented\n", __func__); |
| 797 | panic(); |
| 798 | } |
| 799 | |
| 800 | void plat_marvell_system_reset(void) |
| 801 | { |
| 802 | mmio_write_32(MVEBU_RFU_BASE + MVEBU_RFU_GLOBL_SW_RST, 0x0); |
| 803 | } |
| 804 | |
| 805 | static void __dead2 a8k_system_reset(void) |
| 806 | { |
| 807 | plat_marvell_system_reset(); |
| 808 | |
| 809 | /* we shouldn't get to this point */ |
| 810 | panic(); |
| 811 | } |
| 812 | |
| 813 | /***************************************************************************** |
| 814 | * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard |
| 815 | * platform layer will take care of registering the handlers with PSCI. |
| 816 | ***************************************************************************** |
| 817 | */ |
| 818 | const plat_psci_ops_t plat_arm_psci_pm_ops = { |
| 819 | .cpu_standby = a8k_cpu_standby, |
| 820 | .pwr_domain_on = a8k_pwr_domain_on, |
| 821 | .pwr_domain_off = a8k_pwr_domain_off, |
| 822 | .pwr_domain_suspend = a8k_pwr_domain_suspend, |
| 823 | .pwr_domain_on_finish = a8k_pwr_domain_on_finish, |
| 824 | .get_sys_suspend_power_state = a8k_get_sys_suspend_power_state, |
| 825 | .pwr_domain_suspend_finish = a8k_pwr_domain_suspend_finish, |
| 826 | .pwr_domain_pwr_down_wfi = a8k_pwr_domain_pwr_down_wfi, |
| 827 | .system_off = a8k_system_off, |
| 828 | .system_reset = a8k_system_reset, |
| 829 | .validate_power_state = a8k_validate_power_state, |
| 830 | .validate_ns_entrypoint = a8k_validate_ns_entrypoint |
| 831 | }; |