Soby Mathew | 44170c4 | 2016-03-22 15:51:08 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __XLAT_TABLES_H__ |
| 32 | #define __XLAT_TABLES_H__ |
| 33 | |
| 34 | /* Miscellaneous MMU related constants */ |
Sandrine Bailleux | 072ce13 | 2016-09-15 09:24:54 +0100 | [diff] [blame] | 35 | #define NUM_2MB_IN_GB (1 << 9) |
| 36 | #define NUM_4K_IN_2MB (1 << 9) |
| 37 | #define NUM_GB_IN_4GB (1 << 2) |
| 38 | |
| 39 | #define TWO_MB_SHIFT 21 |
| 40 | #define ONE_GB_SHIFT 30 |
Soby Mathew | 44170c4 | 2016-03-22 15:51:08 +0000 | [diff] [blame] | 41 | #define FOUR_KB_SHIFT 12 |
| 42 | |
Sandrine Bailleux | 072ce13 | 2016-09-15 09:24:54 +0100 | [diff] [blame] | 43 | #define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT) |
| 44 | #define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT) |
| 45 | #define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT) |
| 46 | |
Soby Mathew | 44170c4 | 2016-03-22 15:51:08 +0000 | [diff] [blame] | 47 | #define INVALID_DESC 0x0 |
Antonio Nino Diaz | d48ae61 | 2016-08-02 09:21:41 +0100 | [diff] [blame] | 48 | #define BLOCK_DESC 0x1 /* Table levels 0-2 */ |
| 49 | #define TABLE_DESC 0x3 /* Table levels 0-2 */ |
| 50 | #define PAGE_DESC 0x3 /* Table level 3 */ |
Soby Mathew | 44170c4 | 2016-03-22 15:51:08 +0000 | [diff] [blame] | 51 | |
Sandrine Bailleux | 072ce13 | 2016-09-15 09:24:54 +0100 | [diff] [blame] | 52 | #define FIRST_LEVEL_DESC_N ONE_GB_SHIFT |
| 53 | #define SECOND_LEVEL_DESC_N TWO_MB_SHIFT |
| 54 | #define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT |
| 55 | |
Soby Mathew | 44170c4 | 2016-03-22 15:51:08 +0000 | [diff] [blame] | 56 | #define XN (1ull << 2) |
| 57 | #define PXN (1ull << 1) |
| 58 | #define CONT_HINT (1ull << 0) |
| 59 | |
| 60 | #define UPPER_ATTRS(x) (x & 0x7) << 52 |
| 61 | #define NON_GLOBAL (1 << 9) |
| 62 | #define ACCESS_FLAG (1 << 8) |
| 63 | #define NSH (0x0 << 6) |
| 64 | #define OSH (0x2 << 6) |
| 65 | #define ISH (0x3 << 6) |
| 66 | |
| 67 | #define PAGE_SIZE_SHIFT FOUR_KB_SHIFT |
| 68 | #define PAGE_SIZE (1 << PAGE_SIZE_SHIFT) |
| 69 | #define PAGE_SIZE_MASK (PAGE_SIZE - 1) |
| 70 | #define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0) |
| 71 | |
| 72 | #define XLAT_ENTRY_SIZE_SHIFT 3 /* Each MMU table entry is 8 bytes (1 << 3) */ |
| 73 | #define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SIZE_SHIFT) |
| 74 | |
| 75 | #define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT |
| 76 | #define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT) |
| 77 | |
Antonio Nino Diaz | d48ae61 | 2016-08-02 09:21:41 +0100 | [diff] [blame] | 78 | #ifdef AARCH32 |
| 79 | #define XLAT_TABLE_LEVEL_MIN 1 |
| 80 | #else |
| 81 | #define XLAT_TABLE_LEVEL_MIN 0 |
| 82 | #endif /* AARCH32 */ |
| 83 | |
| 84 | #define XLAT_TABLE_LEVEL_MAX 3 |
| 85 | |
Soby Mathew | 44170c4 | 2016-03-22 15:51:08 +0000 | [diff] [blame] | 86 | /* Values for number of entries in each MMU translation table */ |
| 87 | #define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT) |
| 88 | #define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT) |
| 89 | #define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1) |
| 90 | |
| 91 | /* Values to convert a memory address to an index into a translation table */ |
| 92 | #define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT |
| 93 | #define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) |
| 94 | #define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) |
Antonio Nino Diaz | d48ae61 | 2016-08-02 09:21:41 +0100 | [diff] [blame] | 95 | #define L0_XLAT_ADDRESS_SHIFT (L1_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) |
Antonio Nino Diaz | 46a33a5 | 2016-12-08 16:03:46 +0000 | [diff] [blame^] | 96 | #define XLAT_ADDR_SHIFT(level) (PAGE_SIZE_SHIFT + \ |
| 97 | ((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT)) |
| 98 | |
| 99 | #define XLAT_BLOCK_SIZE(level) ((u_register_t)1 << XLAT_ADDR_SHIFT(level)) |
| 100 | #define XLAT_BLOCK_MASK(level) (XLAT_BLOCK_SIZE(level) - 1) |
Soby Mathew | 44170c4 | 2016-03-22 15:51:08 +0000 | [diff] [blame] | 101 | |
| 102 | /* |
| 103 | * AP[1] bit is ignored by hardware and is |
| 104 | * treated as if it is One in EL2/EL3 |
| 105 | */ |
| 106 | #define AP_RO (0x1 << 5) |
| 107 | #define AP_RW (0x0 << 5) |
| 108 | |
| 109 | #define NS (0x1 << 3) |
| 110 | #define ATTR_NON_CACHEABLE_INDEX 0x2 |
| 111 | #define ATTR_DEVICE_INDEX 0x1 |
| 112 | #define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0 |
| 113 | #define LOWER_ATTRS(x) (((x) & 0xfff) << 2) |
| 114 | #define ATTR_NON_CACHEABLE (0x44) |
| 115 | #define ATTR_DEVICE (0x4) |
| 116 | #define ATTR_IWBWA_OWBWA_NTR (0xff) |
| 117 | #define MAIR_ATTR_SET(attr, index) (attr << (index << 3)) |
| 118 | |
| 119 | /* |
| 120 | * Flags to override default values used to program system registers while |
| 121 | * enabling the MMU. |
| 122 | */ |
| 123 | #define DISABLE_DCACHE (1 << 0) |
| 124 | |
| 125 | #ifndef __ASSEMBLY__ |
| 126 | #include <stddef.h> |
| 127 | #include <stdint.h> |
| 128 | |
| 129 | /* Helper macro to define entries for mmap_region_t. It creates |
| 130 | * identity mappings for each region. |
| 131 | */ |
| 132 | #define MAP_REGION_FLAT(adr, sz, attr) MAP_REGION(adr, adr, sz, attr) |
| 133 | |
| 134 | /* Helper macro to define entries for mmap_region_t. It allows to |
| 135 | * re-map address mappings from 'pa' to 'va' for each region. |
| 136 | */ |
| 137 | #define MAP_REGION(pa, va, sz, attr) {(pa), (va), (sz), (attr)} |
| 138 | |
| 139 | /* |
| 140 | * Shifts and masks to access fields of an mmap_attr_t |
| 141 | */ |
| 142 | #define MT_TYPE_MASK 0x7 |
| 143 | #define MT_TYPE(_attr) ((_attr) & MT_TYPE_MASK) |
| 144 | /* Access permissions (RO/RW) */ |
| 145 | #define MT_PERM_SHIFT 3 |
| 146 | /* Security state (SECURE/NS) */ |
| 147 | #define MT_SEC_SHIFT 4 |
Sandrine Bailleux | ac3aa68 | 2016-06-14 16:31:09 +0100 | [diff] [blame] | 148 | /* Access permissions for instruction execution (EXECUTE/EXECUTE_NEVER) */ |
| 149 | #define MT_EXECUTE_SHIFT 5 |
Soby Mathew | 44170c4 | 2016-03-22 15:51:08 +0000 | [diff] [blame] | 150 | |
| 151 | /* |
| 152 | * Memory mapping attributes |
| 153 | */ |
| 154 | typedef enum { |
| 155 | /* |
| 156 | * Memory types supported. |
| 157 | * These are organised so that, going down the list, the memory types |
| 158 | * are getting weaker; conversely going up the list the memory types are |
| 159 | * getting stronger. |
| 160 | */ |
| 161 | MT_DEVICE, |
| 162 | MT_NON_CACHEABLE, |
| 163 | MT_MEMORY, |
| 164 | /* Values up to 7 are reserved to add new memory types in the future */ |
| 165 | |
Soby Mathew | 44170c4 | 2016-03-22 15:51:08 +0000 | [diff] [blame] | 166 | MT_RO = 0 << MT_PERM_SHIFT, |
| 167 | MT_RW = 1 << MT_PERM_SHIFT, |
| 168 | |
| 169 | MT_SECURE = 0 << MT_SEC_SHIFT, |
| 170 | MT_NS = 1 << MT_SEC_SHIFT, |
Sandrine Bailleux | ac3aa68 | 2016-06-14 16:31:09 +0100 | [diff] [blame] | 171 | |
| 172 | /* |
| 173 | * Access permissions for instruction execution are only relevant for |
| 174 | * normal read-only memory, i.e. MT_MEMORY | MT_RO. They are ignored |
| 175 | * (and potentially overridden) otherwise: |
| 176 | * - Device memory is always marked as execute-never. |
| 177 | * - Read-write normal memory is always marked as execute-never. |
| 178 | */ |
| 179 | MT_EXECUTE = 0 << MT_EXECUTE_SHIFT, |
| 180 | MT_EXECUTE_NEVER = 1 << MT_EXECUTE_SHIFT, |
Soby Mathew | 44170c4 | 2016-03-22 15:51:08 +0000 | [diff] [blame] | 181 | } mmap_attr_t; |
| 182 | |
Sandrine Bailleux | ac3aa68 | 2016-06-14 16:31:09 +0100 | [diff] [blame] | 183 | #define MT_CODE (MT_MEMORY | MT_RO | MT_EXECUTE) |
| 184 | #define MT_RO_DATA (MT_MEMORY | MT_RO | MT_EXECUTE_NEVER) |
| 185 | |
Soby Mathew | 44170c4 | 2016-03-22 15:51:08 +0000 | [diff] [blame] | 186 | /* |
| 187 | * Structure for specifying a single region of memory. |
| 188 | */ |
| 189 | typedef struct mmap_region { |
| 190 | unsigned long long base_pa; |
| 191 | uintptr_t base_va; |
| 192 | size_t size; |
| 193 | mmap_attr_t attr; |
| 194 | } mmap_region_t; |
| 195 | |
| 196 | /* Generic translation table APIs */ |
| 197 | void init_xlat_tables(void); |
| 198 | void mmap_add_region(unsigned long long base_pa, uintptr_t base_va, |
| 199 | size_t size, unsigned int attr); |
| 200 | void mmap_add(const mmap_region_t *mm); |
| 201 | |
Soby Mathew | 935c2e7 | 2016-06-30 15:11:07 +0100 | [diff] [blame] | 202 | #ifdef AARCH32 |
| 203 | /* AArch32 specific translation table API */ |
| 204 | void enable_mmu_secure(uint32_t flags); |
| 205 | #else |
Soby Mathew | 44170c4 | 2016-03-22 15:51:08 +0000 | [diff] [blame] | 206 | /* AArch64 specific translation table APIs */ |
| 207 | void enable_mmu_el1(unsigned int flags); |
| 208 | void enable_mmu_el3(unsigned int flags); |
Soby Mathew | 935c2e7 | 2016-06-30 15:11:07 +0100 | [diff] [blame] | 209 | #endif /* AARCH32 */ |
Soby Mathew | 44170c4 | 2016-03-22 15:51:08 +0000 | [diff] [blame] | 210 | |
| 211 | #endif /*__ASSEMBLY__*/ |
| 212 | #endif /* __XLAT_TABLES_H__ */ |