| Harrison Mutai | e5004c1 | 2023-05-23 17:28:03 +0100 | [diff] [blame] | 1 | /* |
| Bipin Ravi | ad76713 | 2024-01-25 16:18:20 -0600 | [diff] [blame] | 2 | * Copyright (c) 2021-2024, Arm Limited. All rights reserved. |
| Harrison Mutai | e5004c1 | 2023-05-23 17:28:03 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef CORTEX_A715_H |
| 8 | #define CORTEX_A715_H |
| 9 | |
| 10 | #define CORTEX_A715_MIDR U(0x410FD4D0) |
| 11 | |
| 12 | /* Cortex-A715 loop count for CVE-2022-23960 mitigation */ |
| 13 | #define CORTEX_A715_BHB_LOOP_COUNT U(38) |
| 14 | |
| 15 | /******************************************************************************* |
| Bipin Ravi | ad76713 | 2024-01-25 16:18:20 -0600 | [diff] [blame] | 16 | * CPU Auxiliary Control register 2 specific definitions. |
| 17 | ******************************************************************************/ |
| 18 | #define CORTEX_A715_CPUACTLR2_EL1 S3_0_C15_C1_1 |
| 19 | |
| 20 | /******************************************************************************* |
| Harrison Mutai | e5004c1 | 2023-05-23 17:28:03 +0100 | [diff] [blame] | 21 | * CPU Extended Control register specific definitions |
| 22 | ******************************************************************************/ |
| 23 | #define CORTEX_A715_CPUECTLR_EL1 S3_0_C15_C1_4 |
| 24 | |
| Harrison Mutai | 5af4b78 | 2024-01-02 16:55:44 +0000 | [diff] [blame] | 25 | #define CORTEX_A715_CPUPSELR_EL3 S3_6_C15_C8_0 |
| 26 | #define CORTEX_A715_CPUPCR_EL3 S3_6_C15_C8_1 |
| 27 | #define CORTEX_A715_CPUPOR_EL3 S3_6_C15_C8_2 |
| 28 | #define CORTEX_A715_CPUPMR_EL3 S3_6_C15_C8_3 |
| 29 | |
| Harrison Mutai | e5004c1 | 2023-05-23 17:28:03 +0100 | [diff] [blame] | 30 | /******************************************************************************* |
| 31 | * CPU Power Control register specific definitions |
| 32 | ******************************************************************************/ |
| 33 | #define CORTEX_A715_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 34 | #define CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) |
| 35 | |
| 36 | #endif /* CORTEX_A715_H */ |