| Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 1 | /* |
| Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 2 | * Copyright (c) 2020-2022, Arm Limited. All rights reserved. |
| Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef NEOVERSE_N2_H |
| 8 | #define NEOVERSE_N2_H |
| 9 | |
| 10 | /* Neoverse N2 ID register for revision r0p0 */ |
| nayanpatel-arm | d4c5f9c | 2021-09-28 09:46:45 -0700 | [diff] [blame] | 11 | #define NEOVERSE_N2_MIDR U(0x410FD490) |
| Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 12 | |
| Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 13 | /* Neoverse N2 loop count for CVE-2022-23960 mitigation */ |
| 14 | #define NEOVERSE_N2_BHB_LOOP_COUNT U(32) |
| 15 | |
| Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 16 | /******************************************************************************* |
| 17 | * CPU Power control register |
| 18 | ******************************************************************************/ |
| nayanpatel-arm | d4c5f9c | 2021-09-28 09:46:45 -0700 | [diff] [blame] | 19 | #define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 20 | #define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) |
| Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 21 | |
| 22 | /******************************************************************************* |
| 23 | * CPU Extended Control register specific definitions. |
| 24 | ******************************************************************************/ |
| nayanpatel-arm | d4c5f9c | 2021-09-28 09:46:45 -0700 | [diff] [blame] | 25 | #define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 |
| 26 | #define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) |
| 27 | #define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) |
| Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 28 | |
| 29 | /******************************************************************************* |
| 30 | * CPU Auxiliary Control register specific definitions. |
| 31 | ******************************************************************************/ |
| nayanpatel-arm | d4c5f9c | 2021-09-28 09:46:45 -0700 | [diff] [blame] | 32 | #define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 |
| 33 | #define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) |
| nayanpatel-arm | 2f15399 | 2021-10-06 15:31:24 -0700 | [diff] [blame] | 34 | #define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) |
| Bipin Ravi | eb35e85 | 2021-03-30 16:08:32 -0500 | [diff] [blame] | 35 | |
| 36 | /******************************************************************************* |
| 37 | * CPU Auxiliary Control register 2 specific definitions. |
| 38 | ******************************************************************************/ |
| nayanpatel-arm | d4c5f9c | 2021-09-28 09:46:45 -0700 | [diff] [blame] | 39 | #define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 |
| Akram Ahmad | b621bda | 2022-07-18 12:27:29 +0100 | [diff] [blame] | 40 | #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) |
| nayanpatel-arm | d4c5f9c | 2021-09-28 09:46:45 -0700 | [diff] [blame] | 41 | #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) |
| Boyan Karatotev | d3f8b4d | 2022-10-03 14:07:08 +0100 | [diff] [blame] | 42 | #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) |
| Daniel Boulby | 1af2b11 | 2022-07-06 14:33:13 +0100 | [diff] [blame] | 43 | #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) |
| Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 44 | |
| Bipin Ravi | 7e03069 | 2021-08-30 13:02:51 -0500 | [diff] [blame] | 45 | /******************************************************************************* |
| 46 | * CPU Auxiliary Control register 5 specific definitions. |
| 47 | ******************************************************************************/ |
| nayanpatel-arm | d4c5f9c | 2021-09-28 09:46:45 -0700 | [diff] [blame] | 48 | #define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 |
| Arvind Ram Prakash | 465f93b | 2023-07-05 17:24:23 -0500 | [diff] [blame^] | 49 | #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) |
| 50 | #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) |
| nayanpatel-arm | d4c5f9c | 2021-09-28 09:46:45 -0700 | [diff] [blame] | 51 | #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) |
| nayanpatel-arm | 8e1aa01 | 2021-10-20 18:28:58 -0700 | [diff] [blame] | 52 | #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) |
| nayanpatel-arm | fed9813 | 2021-10-07 17:59:33 -0700 | [diff] [blame] | 53 | #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) |
| nayanpatel-arm | d4c5f9c | 2021-09-28 09:46:45 -0700 | [diff] [blame] | 54 | |
| 55 | /******************************************************************************* |
| 56 | * CPU Auxiliary Control register specific definitions. |
| 57 | ******************************************************************************/ |
| 58 | #define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5 |
| 59 | #define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) |
| 60 | #define CPUECTLR2_EL1_PF_MODE_LSB U(11) |
| 61 | #define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) |
| Bipin Ravi | 7e03069 | 2021-08-30 13:02:51 -0500 | [diff] [blame] | 62 | |
| Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 63 | #endif /* NEOVERSE_N2_H */ |