Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 1 | /* |
Paul Beesley | fe975b4 | 2019-09-16 11:29:03 +0000 | [diff] [blame] | 2 | * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Chandni Cherukuri | a3f6613 | 2018-08-10 11:17:58 +0530 | [diff] [blame] | 7 | #ifndef SGI_BASE_PLATFORM_DEF_H |
| 8 | #define SGI_BASE_PLATFORM_DEF_H |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <lib/utils_def.h> |
| 11 | #include <lib/xlat_tables/xlat_tables_defs.h> |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 12 | #include <plat/arm/board/common/board_css_def.h> |
| 13 | #include <plat/arm/board/common/v2m_def.h> |
| 14 | #include <plat/arm/common/arm_def.h> |
| 15 | #include <plat/arm/common/arm_spm_def.h> |
| 16 | #include <plat/arm/css/common/css_def.h> |
| 17 | #include <plat/arm/soc/common/soc_css_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 18 | #include <plat/common/common_def.h> |
| 19 | |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 20 | #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ |
Vishwanatha HG | 64f0b6f | 2018-05-08 17:15:37 +0530 | [diff] [blame] | 21 | CSS_SGI_MAX_CPUS_PER_CLUSTER * \ |
| 22 | CSS_SGI_MAX_PE_PER_CPU) |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 23 | |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 24 | #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ |
| 25 | |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 26 | /* |
| 27 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 28 | * plat_arm_mmap array defined for each BL stage. |
| 29 | */ |
| 30 | #if defined(IMAGE_BL31) |
Paul Beesley | db4e25a | 2019-10-14 15:27:12 +0000 | [diff] [blame] | 31 | # if SPM_MM |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 32 | # define PLAT_ARM_MMAP_ENTRIES 9 |
| 33 | # define MAX_XLAT_TABLES 7 |
| 34 | # define PLAT_SP_IMAGE_MMAP_REGIONS 7 |
| 35 | # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 |
| 36 | # else |
| 37 | # define PLAT_ARM_MMAP_ENTRIES 8 |
| 38 | # define MAX_XLAT_TABLES 5 |
| 39 | # endif |
| 40 | #elif defined(IMAGE_BL32) |
| 41 | # define PLAT_ARM_MMAP_ENTRIES 8 |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 42 | # define MAX_XLAT_TABLES 5 |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 43 | #elif !USE_ROMLIB |
| 44 | # define PLAT_ARM_MMAP_ENTRIES 11 |
| 45 | # define MAX_XLAT_TABLES 5 |
| 46 | #else |
| 47 | # define PLAT_ARM_MMAP_ENTRIES 12 |
| 48 | # define MAX_XLAT_TABLES 6 |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 49 | #endif |
| 50 | |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 51 | /* |
| 52 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 53 | * plus a little space for growth. |
| 54 | */ |
| 55 | #define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000 |
| 56 | |
| 57 | /* |
| 58 | * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page |
| 59 | */ |
| 60 | |
| 61 | #if USE_ROMLIB |
| 62 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 |
| 63 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 64 | #else |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 65 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 |
| 66 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 67 | #endif |
| 68 | |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 69 | /* |
| 70 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 71 | * little space for growth. |
| 72 | */ |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 73 | #if TRUSTED_BOARD_BOOT |
| 74 | # define PLAT_ARM_MAX_BL2_SIZE 0x1D000 |
| 75 | #else |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 76 | # define PLAT_ARM_MAX_BL2_SIZE 0x11000 |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 77 | #endif |
| 78 | |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 79 | /* |
| 80 | * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is |
| 81 | * calculated using the current BL31 PROGBITS debug size plus the sizes of |
| 82 | * BL2 and BL1-RW |
| 83 | */ |
| 84 | #define PLAT_ARM_MAX_BL31_SIZE 0x3B000 |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 85 | |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 86 | /* |
| 87 | * Size of cacheable stacks |
| 88 | */ |
| 89 | #if defined(IMAGE_BL1) |
| 90 | # if TRUSTED_BOARD_BOOT |
| 91 | # define PLATFORM_STACK_SIZE 0x1000 |
| 92 | # else |
| 93 | # define PLATFORM_STACK_SIZE 0x440 |
| 94 | # endif |
| 95 | #elif defined(IMAGE_BL2) |
| 96 | # if TRUSTED_BOARD_BOOT |
| 97 | # define PLATFORM_STACK_SIZE 0x1000 |
| 98 | # else |
| 99 | # define PLATFORM_STACK_SIZE 0x400 |
| 100 | # endif |
| 101 | #elif defined(IMAGE_BL2U) |
| 102 | # define PLATFORM_STACK_SIZE 0x400 |
| 103 | #elif defined(IMAGE_BL31) |
Paul Beesley | db4e25a | 2019-10-14 15:27:12 +0000 | [diff] [blame] | 104 | # if SPM_MM |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 105 | # define PLATFORM_STACK_SIZE 0x500 |
| 106 | # else |
| 107 | # define PLATFORM_STACK_SIZE 0x400 |
| 108 | # endif |
| 109 | #elif defined(IMAGE_BL32) |
| 110 | # define PLATFORM_STACK_SIZE 0x440 |
| 111 | #endif |
| 112 | |
| 113 | |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 114 | #define PLAT_ARM_NSTIMER_FRAME_ID 0 |
| 115 | |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 116 | #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 |
| 117 | #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */ |
| 118 | |
Chris Kay | 42fbdfc | 2018-05-10 14:27:45 +0100 | [diff] [blame] | 119 | #define PLAT_ARM_NSRAM_BASE 0x06000000 |
| 120 | #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ |
| 121 | |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 122 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) |
| 123 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
| 124 | |
| 125 | #define CSS_SGI_DEVICE_BASE (0x20000000) |
| 126 | #define CSS_SGI_DEVICE_SIZE (0x20000000) |
| 127 | #define CSS_SGI_MAP_DEVICE MAP_REGION_FLAT( \ |
| 128 | CSS_SGI_DEVICE_BASE, \ |
| 129 | CSS_SGI_DEVICE_SIZE, \ |
| 130 | MT_DEVICE | MT_RW | MT_SECURE) |
| 131 | |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 132 | /* GIC related constants */ |
| 133 | #define PLAT_ARM_GICD_BASE 0x30000000 |
| 134 | #define PLAT_ARM_GICC_BASE 0x2C000000 |
| 135 | #define PLAT_ARM_GICR_BASE 0x300C0000 |
| 136 | |
Sughosh Ganu | e1579e0 | 2018-05-16 17:19:56 +0530 | [diff] [blame] | 137 | /* Map the secure region for access from S-EL0 */ |
| 138 | #define PLAT_ARM_SECURE_MAP_DEVICE MAP_REGION_FLAT( \ |
| 139 | SOC_CSS_DEVICE_BASE, \ |
| 140 | SOC_CSS_DEVICE_SIZE, \ |
| 141 | MT_DEVICE | MT_RW | MT_SECURE | MT_USER) |
| 142 | |
Sughosh Ganu | d284b57 | 2018-11-14 10:42:46 +0530 | [diff] [blame] | 143 | #define PLAT_SP_PRI PLAT_RAS_PRI |
| 144 | |
Sughosh Ganu | 5f21294 | 2018-05-16 15:35:25 +0530 | [diff] [blame] | 145 | #if RAS_EXTENSION |
| 146 | /* Allocate 128KB for CPER buffers */ |
Sughosh Ganu | 70661cf | 2018-05-16 17:26:40 +0530 | [diff] [blame] | 147 | #define PLAT_SP_BUF_BASE ULL(0x20000) |
| 148 | |
Ard Biesheuvel | 8b034fc | 2018-12-29 19:43:21 +0100 | [diff] [blame] | 149 | #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ |
| 150 | PLAT_SP_IMAGE_NS_BUF_SIZE + \ |
Sughosh Ganu | 70661cf | 2018-05-16 17:26:40 +0530 | [diff] [blame] | 151 | PLAT_SP_BUF_BASE) |
| 152 | |
| 153 | /* Platform specific SMC FID's used for RAS */ |
| 154 | #define SP_DMC_ERROR_INJECT_EVENT_AARCH64 0xC4000042 |
| 155 | #define SP_DMC_ERROR_INJECT_EVENT_AARCH32 0x84000042 |
| 156 | |
| 157 | #define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH64 0xC4000043 |
| 158 | #define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH32 0x84000043 |
| 159 | |
| 160 | #define SP_DMC_ERROR_ECC_EVENT_AARCH64 0xC4000044 |
| 161 | #define SP_DMC_ERROR_ECC_EVENT_AARCH32 0x84000044 |
| 162 | |
| 163 | /* ARM SDEI dynamic shared event numbers */ |
| 164 | #define SGI_SDEI_DS_EVENT_0 804 |
| 165 | #define SGI_SDEI_DS_EVENT_1 805 |
| 166 | |
| 167 | #define PLAT_ARM_PRIVATE_SDEI_EVENTS \ |
| 168 | SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ |
| 169 | SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_0, SDEI_MAPF_CRITICAL), \ |
| 170 | SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_1, SDEI_MAPF_CRITICAL), |
| 171 | #define PLAT_ARM_SHARED_SDEI_EVENTS |
| 172 | |
Ard Biesheuvel | 8b034fc | 2018-12-29 19:43:21 +0100 | [diff] [blame] | 173 | #define ARM_SP_CPER_BUF_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ |
| 174 | PLAT_SP_IMAGE_NS_BUF_SIZE) |
Sughosh Ganu | 70661cf | 2018-05-16 17:26:40 +0530 | [diff] [blame] | 175 | #define ARM_SP_CPER_BUF_SIZE ULL(0x20000) |
| 176 | #define ARM_SP_CPER_BUF_MMAP MAP_REGION2( \ |
| 177 | ARM_SP_CPER_BUF_BASE, \ |
| 178 | ARM_SP_CPER_BUF_BASE, \ |
| 179 | ARM_SP_CPER_BUF_SIZE, \ |
| 180 | MT_RW_DATA | MT_NS | MT_USER, \ |
| 181 | PAGE_SIZE) |
Sughosh Ganu | 5f21294 | 2018-05-16 15:35:25 +0530 | [diff] [blame] | 182 | |
Sughosh Ganu | 5f21294 | 2018-05-16 15:35:25 +0530 | [diff] [blame] | 183 | #else |
Ard Biesheuvel | 8b034fc | 2018-12-29 19:43:21 +0100 | [diff] [blame] | 184 | #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ |
| 185 | PLAT_SP_IMAGE_NS_BUF_SIZE) |
Sughosh Ganu | 5f21294 | 2018-05-16 15:35:25 +0530 | [diff] [blame] | 186 | #endif /* RAS_EXTENSION */ |
| 187 | |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 188 | /* Platform ID address */ |
| 189 | #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) |
Julius Werner | 53456fc | 2019-07-09 13:49:11 -0700 | [diff] [blame] | 190 | #ifndef __ASSEMBLER__ |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 191 | /* SSC_VERSION related accessors */ |
| 192 | /* Returns the part number of the platform */ |
| 193 | #define GET_SGI_PART_NUM \ |
| 194 | GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION)) |
| 195 | /* Returns the configuration number of the platform */ |
| 196 | #define GET_SGI_CONFIG_NUM \ |
| 197 | GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION)) |
Julius Werner | 53456fc | 2019-07-09 13:49:11 -0700 | [diff] [blame] | 198 | #endif /* __ASSEMBLER__ */ |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 199 | |
Roberto Vargas | bcca6c6 | 2018-06-11 16:15:35 +0100 | [diff] [blame] | 200 | /******************************************************************************* |
| 201 | * Memprotect definitions |
| 202 | ******************************************************************************/ |
| 203 | /* PSCI memory protect definitions: |
| 204 | * This variable is stored in a non-secure flash because some ARM reference |
| 205 | * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT |
| 206 | * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. |
| 207 | */ |
| 208 | #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ |
| 209 | V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) |
| 210 | |
Aditya Angadi | 20b4841 | 2019-04-16 11:29:14 +0530 | [diff] [blame] | 211 | /*Secure Watchdog Constants */ |
| 212 | #define SBSA_SECURE_WDOG_BASE UL(0x2A480000) |
| 213 | #define SBSA_SECURE_WDOG_TIMEOUT UL(100) |
Roberto Vargas | bcca6c6 | 2018-06-11 16:15:35 +0100 | [diff] [blame] | 214 | |
Chandni Cherukuri | a3f6613 | 2018-08-10 11:17:58 +0530 | [diff] [blame] | 215 | #endif /* SGI_BASE_PLATFORM_DEF_H */ |