Usama Arif | 82e9509 | 2019-06-18 16:46:05 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| 10 | #include <common/tbbr/tbbr_img_def.h> |
| 11 | #include <lib/utils_def.h> |
| 12 | #include <lib/xlat_tables/xlat_tables_defs.h> |
| 13 | #include <plat/arm/board/common/v2m_def.h> |
| 14 | #include <plat/common/common_def.h> |
| 15 | |
| 16 | /* Memory location options for TSP */ |
| 17 | #define ARM_DRAM_ID 2 |
| 18 | |
| 19 | #define ARM_DRAM1_BASE UL(0x80000000) |
| 20 | #define ARM_DRAM1_SIZE UL(0x80000000) |
| 21 | #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ |
| 22 | ARM_DRAM1_SIZE - 1) |
| 23 | |
| 24 | #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE |
| 25 | /* |
| 26 | * The last 2MB is meant to be NOLOAD and will not be zero |
| 27 | * initialized. |
| 28 | */ |
| 29 | #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ |
| 30 | 0x00200000) |
| 31 | |
| 32 | #define SRAM_BASE 0x2000000 |
| 33 | #define SRAM_SIZE 0x200000 |
| 34 | |
| 35 | /* The first 4KB of NS DRAM1 are used as shared memory */ |
| 36 | #define A5DS_SHARED_RAM_BASE SRAM_BASE |
| 37 | #define A5DS_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ |
| 38 | |
| 39 | /* The next 252 kB of NS DRAM is used to load the BL images */ |
| 40 | #define ARM_BL_RAM_BASE (A5DS_SHARED_RAM_BASE + \ |
| 41 | A5DS_SHARED_RAM_SIZE) |
| 42 | #define ARM_BL_RAM_SIZE (PLAT_ARM_BL_PLUS_SHARED_RAM_SIZE - \ |
| 43 | A5DS_SHARED_RAM_SIZE) |
| 44 | |
| 45 | #define PERIPHBASE 0x1a000000 |
| 46 | #define PERIPH_SIZE 0x00240000 |
| 47 | #define A5_PERIPHERALS_BASE 0x1c000000 |
| 48 | #define A5_PERIPHERALS_SIZE 0x10000 |
| 49 | |
| 50 | #define ARM_CACHE_WRITEBACK_SHIFT 6 |
| 51 | |
| 52 | #define ARM_IRQ_SEC_PHY_TIMER 29 |
| 53 | |
| 54 | #define ARM_IRQ_SEC_SGI_0 8 |
| 55 | #define ARM_IRQ_SEC_SGI_1 9 |
| 56 | #define ARM_IRQ_SEC_SGI_2 10 |
| 57 | #define ARM_IRQ_SEC_SGI_3 11 |
| 58 | #define ARM_IRQ_SEC_SGI_4 12 |
| 59 | #define ARM_IRQ_SEC_SGI_5 13 |
| 60 | #define ARM_IRQ_SEC_SGI_6 14 |
| 61 | #define ARM_IRQ_SEC_SGI_7 15 |
| 62 | |
| 63 | /* |
| 64 | * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 |
| 65 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 66 | * as Group 0 interrupts. |
| 67 | */ |
| 68 | #define ARM_G1S_IRQ_PROPS(grp) \ |
| 69 | INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 70 | GIC_INTR_CFG_LEVEL), \ |
| 71 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 72 | GIC_INTR_CFG_EDGE), \ |
| 73 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 74 | GIC_INTR_CFG_EDGE), \ |
| 75 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 76 | GIC_INTR_CFG_EDGE), \ |
| 77 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 78 | GIC_INTR_CFG_EDGE), \ |
| 79 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 80 | GIC_INTR_CFG_EDGE), \ |
| 81 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 82 | GIC_INTR_CFG_EDGE) |
| 83 | |
| 84 | #define ARM_G0_IRQ_PROPS(grp) \ |
| 85 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 86 | GIC_INTR_CFG_EDGE) |
| 87 | |
| 88 | #define A5DS_IRQ_TZ_WDOG 56 |
| 89 | #define A5DS_IRQ_SEC_SYS_TIMER 57 |
| 90 | |
| 91 | /* Default cluster count for A5DS */ |
| 92 | #define A5DS_CLUSTER_COUNT 1 |
| 93 | |
| 94 | /* Default number of CPUs per cluster on A5DS */ |
| 95 | #define A5DS_MAX_CPUS_PER_CLUSTER 4 |
| 96 | |
| 97 | /* Default number of threads per CPU on A5DS */ |
| 98 | #define A5DS_MAX_PE_PER_CPU 1 |
| 99 | |
Usama Arif | 79913a8 | 2019-09-19 11:07:24 +0100 | [diff] [blame] | 100 | #define A5DS_CORE_COUNT 4 |
Usama Arif | 82e9509 | 2019-06-18 16:46:05 +0100 | [diff] [blame] | 101 | |
Usama Arif | 79913a8 | 2019-09-19 11:07:24 +0100 | [diff] [blame] | 102 | #define A5DS_PRIMARY_CPU 0x0 |
Usama Arif | 82e9509 | 2019-06-18 16:46:05 +0100 | [diff] [blame] | 103 | |
| 104 | #define FLASH1_BASE UL(0x8000000) |
| 105 | #define FLASH1_SIZE UL(0x2800000) |
| 106 | |
| 107 | #define MAP_FLASH1_RW MAP_REGION_FLAT(FLASH1_BASE,\ |
| 108 | FLASH1_SIZE, \ |
| 109 | MT_DEVICE | MT_RW | MT_SECURE) |
| 110 | |
| 111 | #define MAP_FLASH1_RO MAP_REGION_FLAT(FLASH1_BASE,\ |
| 112 | FLASH1_SIZE, \ |
| 113 | MT_RO_DATA | MT_SECURE) |
| 114 | |
| 115 | #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ |
| 116 | A5DS_SHARED_RAM_BASE, \ |
| 117 | A5DS_SHARED_RAM_SIZE, \ |
| 118 | MT_MEMORY | MT_RW | MT_SECURE) |
| 119 | |
| 120 | #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ |
| 121 | ARM_NS_DRAM1_BASE, \ |
| 122 | ARM_NS_DRAM1_SIZE, \ |
| 123 | MT_MEMORY | MT_RW | MT_NS) |
| 124 | |
| 125 | #define ARM_MAP_SRAM MAP_REGION_FLAT( \ |
| 126 | SRAM_BASE, \ |
| 127 | SRAM_SIZE, \ |
| 128 | MT_MEMORY | MT_RW | MT_NS) |
| 129 | |
| 130 | /* |
| 131 | * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to |
| 132 | * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides |
| 133 | * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order |
| 134 | * to be able to access the heap. |
| 135 | */ |
| 136 | |
| 137 | #define ARM_MAP_BL_RO MAP_REGION_FLAT(\ |
| 138 | BL_CODE_BASE,\ |
| 139 | BL_CODE_END - BL_CODE_BASE,\ |
| 140 | MT_CODE | MT_SECURE),\ |
| 141 | MAP_REGION_FLAT(\ |
| 142 | BL_RO_DATA_BASE,\ |
| 143 | BL_RO_DATA_END\ |
| 144 | - BL_RO_DATA_BASE, \ |
| 145 | MT_RO_DATA | MT_SECURE) |
| 146 | |
| 147 | #if USE_COHERENT_MEM |
| 148 | #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT(\ |
| 149 | BL_COHERENT_RAM_BASE,\ |
| 150 | BL_COHERENT_RAM_END \ |
| 151 | - BL_COHERENT_RAM_BASE, \ |
| 152 | MT_DEVICE | MT_RW | MT_SECURE) |
| 153 | #endif |
| 154 | |
| 155 | /* |
| 156 | * The max number of regions like RO(code), coherent and data required by |
| 157 | * different BL stages which need to be mapped in the MMU. |
| 158 | */ |
| 159 | #define ARM_BL_REGIONS 5 |
| 160 | |
| 161 | #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ |
| 162 | ARM_BL_REGIONS) |
| 163 | |
| 164 | /* Memory mapped Generic timer interfaces */ |
| 165 | #define A5DS_TIMER_BASE_FREQUENCY UL(24000000) |
| 166 | |
| 167 | #define ARM_CONSOLE_BAUDRATE 115200 |
| 168 | |
| 169 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 170 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
| 171 | |
| 172 | /* |
| 173 | * This macro defines the deepest retention state possible. A higher state |
| 174 | * id will represent an invalid or a power down state. |
| 175 | */ |
| 176 | #define PLAT_MAX_RET_STATE 1 |
| 177 | |
| 178 | /* |
| 179 | * This macro defines the deepest power down states possible. Any state ID |
| 180 | * higher than this is invalid. |
| 181 | */ |
| 182 | #define PLAT_MAX_OFF_STATE 2 |
| 183 | |
| 184 | /* |
| 185 | * Some data must be aligned on the biggest cache line size in the platform. |
| 186 | * This is known only to the platform as it might have a combination of |
| 187 | * integrated and external caches. |
| 188 | */ |
| 189 | #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) |
| 190 | |
| 191 | /* |
| 192 | * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base |
| 193 | * and limit. Leave enough space of BL2 meminfo. |
| 194 | */ |
| 195 | #define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) |
| 196 | #define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE) |
| 197 | |
| 198 | /******************************************************************************* |
| 199 | * BL1 specific defines. |
| 200 | * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of |
| 201 | * addresses. |
| 202 | ******************************************************************************/ |
| 203 | #define BL1_RO_BASE 0x00000000 |
| 204 | #define BL1_RO_LIMIT PLAT_ARM_TRUSTED_ROM_SIZE |
| 205 | /* |
| 206 | * Put BL1 RW at the top of the memory allocated for BL images in NS DRAM. |
| 207 | */ |
| 208 | #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ |
| 209 | ARM_BL_RAM_SIZE - \ |
| 210 | (PLAT_ARM_MAX_BL1_RW_SIZE)) |
| 211 | #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ |
| 212 | (ARM_BL_RAM_SIZE)) |
| 213 | /******************************************************************************* |
| 214 | * BL2 specific defines. |
| 215 | ******************************************************************************/ |
| 216 | |
| 217 | /* |
| 218 | * Put BL2 just below BL1. |
| 219 | */ |
| 220 | #define BL2_BASE (BL1_RW_BASE - A5DS_MAX_BL2_SIZE) |
| 221 | #define BL2_LIMIT BL1_RW_BASE |
| 222 | |
| 223 | /* Put BL32 below BL2 in NS DRAM.*/ |
| 224 | #define ARM_BL2_MEM_DESC_BASE ARM_TB_FW_CONFIG_LIMIT |
| 225 | |
| 226 | #define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ |
| 227 | - PLAT_ARM_MAX_BL32_SIZE) |
| 228 | #define BL32_PROGBITS_LIMIT BL2_BASE |
| 229 | #define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) |
| 230 | |
| 231 | /* Required platform porting definitions */ |
Usama Arif | 79913a8 | 2019-09-19 11:07:24 +0100 | [diff] [blame] | 232 | #define PLATFORM_CORE_COUNT A5DS_CORE_COUNT |
| 233 | #define PLAT_NUM_PWR_DOMAINS (A5DS_CLUSTER_COUNT + \ |
Usama Arif | 82e9509 | 2019-06-18 16:46:05 +0100 | [diff] [blame] | 234 | PLATFORM_CORE_COUNT) + 1 |
| 235 | |
Usama Arif | 79913a8 | 2019-09-19 11:07:24 +0100 | [diff] [blame] | 236 | #define PLAT_MAX_PWR_LVL 2 |
Usama Arif | 82e9509 | 2019-06-18 16:46:05 +0100 | [diff] [blame] | 237 | |
| 238 | /* |
| 239 | * Other platform porting definitions are provided by included headers |
| 240 | */ |
| 241 | |
| 242 | /* |
| 243 | * Required ARM standard platform porting definitions |
| 244 | */ |
| 245 | |
| 246 | #define PLAT_ARM_BL_PLUS_SHARED_RAM_SIZE 0x00040000 /* 256 KB */ |
| 247 | |
| 248 | #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 |
| 249 | #define PLAT_ARM_TRUSTED_ROM_SIZE 0x10000 /* 64KB */ |
| 250 | |
| 251 | #define PLAT_ARM_DRAM2_SIZE ULL(0x80000000) |
| 252 | |
| 253 | /* |
| 254 | * Load address of BL33 for this platform port |
| 255 | */ |
| 256 | #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + U(0x8000000)) |
| 257 | |
| 258 | /* |
| 259 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 260 | * plat_arm_mmap array defined for each BL stage. |
| 261 | */ |
| 262 | #if defined(IMAGE_BL32) |
| 263 | # define PLAT_ARM_MMAP_ENTRIES 8 |
| 264 | # define MAX_XLAT_TABLES 6 |
| 265 | #else |
| 266 | # define PLAT_ARM_MMAP_ENTRIES 12 |
| 267 | # define MAX_XLAT_TABLES 6 |
| 268 | #endif |
| 269 | |
| 270 | /* |
| 271 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 272 | * plus a little space for growth. |
| 273 | */ |
| 274 | #define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000 |
| 275 | |
| 276 | /* |
| 277 | * A5DS_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 278 | * little space for growth. |
| 279 | */ |
| 280 | #define A5DS_MAX_BL2_SIZE 0x11000 |
| 281 | |
| 282 | /* |
| 283 | * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is |
| 284 | * calculated using the current SP_MIN PROGBITS debug size plus the sizes of |
| 285 | * BL2 and BL1-RW |
| 286 | */ |
| 287 | #define PLAT_ARM_MAX_BL32_SIZE 0x3B000 |
| 288 | /* |
| 289 | * Size of cacheable stacks |
| 290 | */ |
| 291 | #if defined(IMAGE_BL1) |
| 292 | # define PLATFORM_STACK_SIZE 0x440 |
| 293 | #elif defined(IMAGE_BL2) |
| 294 | # define PLATFORM_STACK_SIZE 0x400 |
| 295 | #elif defined(IMAGE_BL32) |
| 296 | # define PLATFORM_STACK_SIZE 0x440 |
| 297 | #endif |
| 298 | |
| 299 | #define MAX_IO_DEVICES 3 |
| 300 | #define MAX_IO_HANDLES 4 |
| 301 | |
| 302 | /* Reserve the last block of flash for PSCI MEM PROTECT flag */ |
| 303 | #define PLAT_ARM_FIP_BASE FLASH1_BASE |
| 304 | #define PLAT_ARM_FIP_MAX_SIZE (FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE) |
| 305 | |
| 306 | #define PLAT_ARM_NVM_BASE FLASH1_BASE |
| 307 | #define PLAT_ARM_NVM_SIZE (FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE) |
| 308 | |
| 309 | /* |
| 310 | * PL011 related constants |
| 311 | */ |
| 312 | #define PLAT_ARM_BOOT_UART_BASE 0x1A200000 |
| 313 | #define PLAT_ARM_BOOT_UART_CLK_IN_HZ 24000000 |
| 314 | |
| 315 | #define PLAT_ARM_RUN_UART_BASE 0x1A210000 |
| 316 | #define PLAT_ARM_RUN_UART_CLK_IN_HZ 24000000 |
| 317 | |
| 318 | #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE |
| 319 | #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ |
| 320 | |
| 321 | #define A5DS_TIMER_BASE_FREQUENCY UL(24000000) |
| 322 | |
| 323 | /* System timer related constants */ |
| 324 | #define PLAT_ARM_NSTIMER_FRAME_ID 1 |
| 325 | |
| 326 | /* Mailbox base address */ |
| 327 | #define A5DS_TRUSTED_MAILBOX_BASE A5DS_SHARED_RAM_BASE |
Usama Arif | 0cf7913 | 2019-09-19 10:54:16 +0100 | [diff] [blame] | 328 | #define A5DS_TRUSTED_MAILBOX_SIZE (8 + A5DS_HOLD_SIZE) |
| 329 | #define A5DS_HOLD_BASE (A5DS_TRUSTED_MAILBOX_BASE + 8) |
| 330 | #define A5DS_HOLD_SIZE (PLATFORM_CORE_COUNT * \ |
| 331 | A5DS_HOLD_ENTRY_SIZE) |
| 332 | #define A5DS_HOLD_ENTRY_SHIFT 3 |
| 333 | #define A5DS_HOLD_ENTRY_SIZE (1 << A5DS_HOLD_ENTRY_SHIFT) |
| 334 | #define A5DS_HOLD_STATE_WAIT 0 |
| 335 | #define A5DS_HOLD_STATE_GO 1 |
Usama Arif | 82e9509 | 2019-06-18 16:46:05 +0100 | [diff] [blame] | 336 | |
| 337 | /* |
| 338 | * GIC related constants to cater for GICv2 |
| 339 | */ |
| 340 | #define PLAT_ARM_GICD_BASE 0x1C001000 |
| 341 | #define PLAT_ARM_GICC_BASE 0x1C000100 |
| 342 | |
| 343 | /* |
| 344 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 345 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 346 | * as Group 0 interrupts. |
| 347 | */ |
| 348 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 349 | ARM_G1S_IRQ_PROPS(grp), \ |
| 350 | INTR_PROP_DESC(A5DS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 351 | GIC_INTR_CFG_LEVEL), \ |
| 352 | INTR_PROP_DESC(A5DS_IRQ_SEC_SYS_TIMER,\ |
| 353 | GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 354 | GIC_INTR_CFG_LEVEL) |
| 355 | |
| 356 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
| 357 | |
| 358 | #endif /* PLATFORM_DEF_H */ |