Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 1 | /* |
Yann Gautier | a0a6ff6 | 2021-05-10 16:05:18 +0200 | [diff] [blame] | 2 | * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef STM32MP_COMMON_H |
| 8 | #define STM32MP_COMMON_H |
| 9 | |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 10 | #include <stdbool.h> |
| 11 | |
Yann Gautier | e97b663 | 2019-04-19 10:48:36 +0200 | [diff] [blame] | 12 | #include <platform_def.h> |
| 13 | |
Yann Gautier | ed6515d | 2021-03-08 15:03:35 +0100 | [diff] [blame] | 14 | #define JEDEC_ST_BKID U(0x0) |
| 15 | #define JEDEC_ST_MFID U(0x20) |
| 16 | |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 17 | /* Functions to save and get boot context address given by ROM code */ |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 18 | void stm32mp_save_boot_ctx_address(uintptr_t address); |
| 19 | uintptr_t stm32mp_get_boot_ctx_address(void); |
Yann Gautier | cf1360d | 2020-08-27 18:28:57 +0200 | [diff] [blame] | 20 | uint16_t stm32mp_get_boot_itf_selected(void); |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 21 | |
Yann Gautier | af19ff9 | 2019-06-04 18:23:10 +0200 | [diff] [blame] | 22 | bool stm32mp_is_single_core(void); |
Lionel Debieve | 0e73d73 | 2019-09-16 12:17:09 +0200 | [diff] [blame] | 23 | bool stm32mp_is_closed_device(void); |
Yann Gautier | af19ff9 | 2019-06-04 18:23:10 +0200 | [diff] [blame] | 24 | |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 25 | /* Return the base address of the DDR controller */ |
| 26 | uintptr_t stm32mp_ddrctrl_base(void); |
| 27 | |
| 28 | /* Return the base address of the DDR PHY */ |
| 29 | uintptr_t stm32mp_ddrphyc_base(void); |
| 30 | |
| 31 | /* Return the base address of the PWR peripheral */ |
| 32 | uintptr_t stm32mp_pwr_base(void); |
| 33 | |
| 34 | /* Return the base address of the RCC peripheral */ |
| 35 | uintptr_t stm32mp_rcc_base(void); |
| 36 | |
Yann Gautier | f540a59 | 2019-05-22 19:13:51 +0200 | [diff] [blame] | 37 | /* Check MMU status to allow spinlock use */ |
| 38 | bool stm32mp_lock_available(void); |
| 39 | |
Yann Gautier | 091eab5 | 2019-06-04 18:06:34 +0200 | [diff] [blame] | 40 | /* Get IWDG platform instance ID from peripheral IO memory base address */ |
| 41 | uint32_t stm32_iwdg_get_instance(uintptr_t base); |
| 42 | |
| 43 | /* Return bitflag mask for expected IWDG configuration from OTP content */ |
| 44 | uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst); |
| 45 | |
| 46 | #if defined(IMAGE_BL2) |
| 47 | /* Update OTP shadow registers with IWDG configuration from device tree */ |
| 48 | uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags); |
| 49 | #endif |
| 50 | |
Yann Gautier | 3d8497c | 2021-10-18 16:06:22 +0200 | [diff] [blame] | 51 | #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) |
Patrick Delaunay | e50571b | 2021-10-28 13:48:52 +0200 | [diff] [blame] | 52 | /* Get the UART address from its instance number */ |
| 53 | uintptr_t get_uart_address(uint32_t instance_nb); |
| 54 | #endif |
| 55 | |
Yann Gautier | 7a81912 | 2021-10-18 15:26:33 +0200 | [diff] [blame] | 56 | /* Setup the UART console */ |
| 57 | int stm32mp_uart_console_setup(void); |
| 58 | |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 59 | /* |
| 60 | * Platform util functions for the GPIO driver |
| 61 | * @bank: Target GPIO bank ID as per DT bindings |
| 62 | * |
| 63 | * Platform shall implement these functions to provide to stm32_gpio |
| 64 | * driver the resource reference for a target GPIO bank. That are |
| 65 | * memory mapped interface base address, interface offset (see below) |
| 66 | * and clock identifier. |
| 67 | * |
| 68 | * stm32_get_gpio_bank_offset() returns a bank offset that is used to |
| 69 | * check DT configuration matches platform implementation of the banks |
| 70 | * description. |
| 71 | */ |
| 72 | uintptr_t stm32_get_gpio_bank_base(unsigned int bank); |
| 73 | unsigned long stm32_get_gpio_bank_clock(unsigned int bank); |
| 74 | uint32_t stm32_get_gpio_bank_offset(unsigned int bank); |
Yann Gautier | 2b79c37 | 2021-06-11 10:54:56 +0200 | [diff] [blame] | 75 | bool stm32_gpio_is_secure_at_reset(unsigned int bank); |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 76 | |
Etienne Carriere | d81dadf | 2020-04-25 11:14:45 +0200 | [diff] [blame] | 77 | /* Return node offset for target GPIO bank ID @bank or a FDT error code */ |
| 78 | int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank); |
| 79 | |
Yann Gautier | a0a6ff6 | 2021-05-10 16:05:18 +0200 | [diff] [blame] | 80 | /* Get the chip revision */ |
| 81 | uint32_t stm32mp_get_chip_version(void); |
| 82 | /* Get the chip device ID */ |
| 83 | uint32_t stm32mp_get_chip_dev_id(void); |
| 84 | |
| 85 | /* Get SOC name */ |
| 86 | #define STM32_SOC_NAME_SIZE 20 |
| 87 | void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]); |
| 88 | |
Yann Gautier | c737405 | 2019-06-04 18:02:37 +0200 | [diff] [blame] | 89 | /* Print CPU information */ |
| 90 | void stm32mp_print_cpuinfo(void); |
| 91 | |
Yann Gautier | 35dc077 | 2019-05-13 18:34:48 +0200 | [diff] [blame] | 92 | /* Print board information */ |
| 93 | void stm32mp_print_boardinfo(void); |
| 94 | |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 95 | /* |
| 96 | * Util for clock gating and to get clock rate for stm32 and platform drivers |
| 97 | * @id: Target clock ID, ID used in clock DT bindings |
| 98 | */ |
| 99 | bool stm32mp_clk_is_enabled(unsigned long id); |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 100 | void stm32mp_clk_enable(unsigned long id); |
| 101 | void stm32mp_clk_disable(unsigned long id); |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 102 | unsigned long stm32mp_clk_get_rate(unsigned long id); |
| 103 | |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 104 | /* Initialise the IO layer and register platform IO devices */ |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 105 | void stm32mp_io_setup(void); |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 106 | |
Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 107 | #if STM32MP_USE_STM32IMAGE |
Yann Gautier | e97b663 | 2019-04-19 10:48:36 +0200 | [diff] [blame] | 108 | /* |
| 109 | * Check that the STM32 header of a .stm32 binary image is valid |
| 110 | * @param header: pointer to the stm32 image header |
| 111 | * @param buffer: address of the binary image (payload) |
| 112 | * @return: 0 on success, negative value in case of error |
| 113 | */ |
| 114 | int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer); |
Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 115 | #endif /* STM32MP_USE_STM32IMAGE */ |
Yann Gautier | e97b663 | 2019-04-19 10:48:36 +0200 | [diff] [blame] | 116 | |
Yann Gautier | a55169b | 2020-01-10 18:18:59 +0100 | [diff] [blame] | 117 | /* Functions to map DDR in MMU with non-cacheable attribute, and unmap it */ |
| 118 | int stm32mp_map_ddr_non_cacheable(void); |
| 119 | int stm32mp_unmap_ddr(void); |
| 120 | |
Yann Gautier | aaee061 | 2020-12-16 12:04:06 +0100 | [diff] [blame] | 121 | /* Functions to save and get boot peripheral info */ |
Yann Gautier | 6eef525 | 2021-12-10 17:04:40 +0100 | [diff] [blame] | 122 | void stm32_save_boot_interface(uint32_t interface, uint32_t instance); |
Yann Gautier | aaee061 | 2020-12-16 12:04:06 +0100 | [diff] [blame] | 123 | void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance); |
Yann Gautier | 6eef525 | 2021-12-10 17:04:40 +0100 | [diff] [blame] | 124 | |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 125 | #endif /* STM32MP_COMMON_H */ |