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Yann Gautieree8f5422019-02-14 11:13:25 +01001/*
Yann Gautiera0a6ff62021-05-10 16:05:18 +02002 * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved
Yann Gautieree8f5422019-02-14 11:13:25 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef STM32MP_COMMON_H
8#define STM32MP_COMMON_H
9
Yann Gautiera2e2a302019-02-14 11:13:39 +010010#include <stdbool.h>
11
Yann Gautiere97b6632019-04-19 10:48:36 +020012#include <platform_def.h>
13
Yann Gautiered6515d2021-03-08 15:03:35 +010014#define JEDEC_ST_BKID U(0x0)
15#define JEDEC_ST_MFID U(0x20)
16
Yann Gautieree8f5422019-02-14 11:13:25 +010017/* Functions to save and get boot context address given by ROM code */
Yann Gautiera2e2a302019-02-14 11:13:39 +010018void stm32mp_save_boot_ctx_address(uintptr_t address);
19uintptr_t stm32mp_get_boot_ctx_address(void);
Yann Gautiercf1360d2020-08-27 18:28:57 +020020uint16_t stm32mp_get_boot_itf_selected(void);
Yann Gautieree8f5422019-02-14 11:13:25 +010021
Yann Gautieraf19ff92019-06-04 18:23:10 +020022bool stm32mp_is_single_core(void);
Lionel Debieve0e73d732019-09-16 12:17:09 +020023bool stm32mp_is_closed_device(void);
Yann Gautieraf19ff92019-06-04 18:23:10 +020024
Yann Gautier3d78a2e2019-02-14 11:01:20 +010025/* Return the base address of the DDR controller */
26uintptr_t stm32mp_ddrctrl_base(void);
27
28/* Return the base address of the DDR PHY */
29uintptr_t stm32mp_ddrphyc_base(void);
30
31/* Return the base address of the PWR peripheral */
32uintptr_t stm32mp_pwr_base(void);
33
34/* Return the base address of the RCC peripheral */
35uintptr_t stm32mp_rcc_base(void);
36
Yann Gautierf540a592019-05-22 19:13:51 +020037/* Check MMU status to allow spinlock use */
38bool stm32mp_lock_available(void);
39
Yann Gautier091eab52019-06-04 18:06:34 +020040/* Get IWDG platform instance ID from peripheral IO memory base address */
41uint32_t stm32_iwdg_get_instance(uintptr_t base);
42
43/* Return bitflag mask for expected IWDG configuration from OTP content */
44uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst);
45
46#if defined(IMAGE_BL2)
47/* Update OTP shadow registers with IWDG configuration from device tree */
48uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags);
49#endif
50
Yann Gautier3d8497c2021-10-18 16:06:22 +020051#if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2)
Patrick Delaunaye50571b2021-10-28 13:48:52 +020052/* Get the UART address from its instance number */
53uintptr_t get_uart_address(uint32_t instance_nb);
54#endif
55
Yann Gautier7a819122021-10-18 15:26:33 +020056/* Setup the UART console */
57int stm32mp_uart_console_setup(void);
58
Yann Gautieree8f5422019-02-14 11:13:25 +010059/*
60 * Platform util functions for the GPIO driver
61 * @bank: Target GPIO bank ID as per DT bindings
62 *
63 * Platform shall implement these functions to provide to stm32_gpio
64 * driver the resource reference for a target GPIO bank. That are
65 * memory mapped interface base address, interface offset (see below)
66 * and clock identifier.
67 *
68 * stm32_get_gpio_bank_offset() returns a bank offset that is used to
69 * check DT configuration matches platform implementation of the banks
70 * description.
71 */
72uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
73unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
74uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
Yann Gautier2b79c372021-06-11 10:54:56 +020075bool stm32_gpio_is_secure_at_reset(unsigned int bank);
Yann Gautieree8f5422019-02-14 11:13:25 +010076
Etienne Carriered81dadf2020-04-25 11:14:45 +020077/* Return node offset for target GPIO bank ID @bank or a FDT error code */
78int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank);
79
Yann Gautiera0a6ff62021-05-10 16:05:18 +020080/* Get the chip revision */
81uint32_t stm32mp_get_chip_version(void);
82/* Get the chip device ID */
83uint32_t stm32mp_get_chip_dev_id(void);
84
85/* Get SOC name */
86#define STM32_SOC_NAME_SIZE 20
87void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]);
88
Yann Gautierc7374052019-06-04 18:02:37 +020089/* Print CPU information */
90void stm32mp_print_cpuinfo(void);
91
Yann Gautier35dc0772019-05-13 18:34:48 +020092/* Print board information */
93void stm32mp_print_boardinfo(void);
94
Yann Gautiera2e2a302019-02-14 11:13:39 +010095/*
96 * Util for clock gating and to get clock rate for stm32 and platform drivers
97 * @id: Target clock ID, ID used in clock DT bindings
98 */
99bool stm32mp_clk_is_enabled(unsigned long id);
Yann Gautiere4a3c352019-02-14 10:53:33 +0100100void stm32mp_clk_enable(unsigned long id);
101void stm32mp_clk_disable(unsigned long id);
Yann Gautiera2e2a302019-02-14 11:13:39 +0100102unsigned long stm32mp_clk_get_rate(unsigned long id);
103
Yann Gautieree8f5422019-02-14 11:13:25 +0100104/* Initialise the IO layer and register platform IO devices */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100105void stm32mp_io_setup(void);
Yann Gautieree8f5422019-02-14 11:13:25 +0100106
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200107#if STM32MP_USE_STM32IMAGE
Yann Gautiere97b6632019-04-19 10:48:36 +0200108/*
109 * Check that the STM32 header of a .stm32 binary image is valid
110 * @param header: pointer to the stm32 image header
111 * @param buffer: address of the binary image (payload)
112 * @return: 0 on success, negative value in case of error
113 */
114int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer);
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200115#endif /* STM32MP_USE_STM32IMAGE */
Yann Gautiere97b6632019-04-19 10:48:36 +0200116
Yann Gautiera55169b2020-01-10 18:18:59 +0100117/* Functions to map DDR in MMU with non-cacheable attribute, and unmap it */
118int stm32mp_map_ddr_non_cacheable(void);
119int stm32mp_unmap_ddr(void);
120
Yann Gautieraaee0612020-12-16 12:04:06 +0100121/* Functions to save and get boot peripheral info */
Yann Gautier6eef5252021-12-10 17:04:40 +0100122void stm32_save_boot_interface(uint32_t interface, uint32_t instance);
Yann Gautieraaee0612020-12-16 12:04:06 +0100123void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance);
Yann Gautier6eef5252021-12-10 17:04:40 +0100124
Yann Gautieree8f5422019-02-14 11:13:25 +0100125#endif /* STM32MP_COMMON_H */