| Govindraj Raja | e63794e | 2024-09-06 15:43:43 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2024, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <lib/extensions/sysreg128.h> |
| 10 | |
| 11 | .global read_par_el1 |
| 12 | .global write_par_el1 |
| 13 | .global read_ttbr0_el1 |
| 14 | .global write_ttbr0_el1 |
| 15 | .global read_ttbr1_el1 |
| 16 | .global write_ttbr1_el1 |
| 17 | .global read_ttbr0_el2 |
| 18 | .global write_ttbr0_el2 |
| 19 | .global read_ttbr1_el2 |
| 20 | .global write_ttbr1_el2 |
| 21 | .global read_vttbr_el2 |
| 22 | .global write_vttbr_el2 |
| 23 | .global read_rcwmask_el1 |
| 24 | .global write_rcwmask_el1 |
| 25 | .global read_rcwsmask_el1 |
| 26 | .global write_rcwsmask_el1 |
| 27 | |
| 28 | /* |
| 29 | * _mrrs - Move System register to two adjacent general-purpose |
| 30 | * registers. |
| 31 | * Instruction: MRRS <Xt>, <Xt+1>, (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>) |
| 32 | * |
| 33 | * Arguments/Opcode bit field: |
| 34 | * regins: System register opcode. |
| 35 | * |
| 36 | * Clobbers: x0,x1,x2 |
| 37 | */ |
| 38 | .macro _mrrs regins:req |
| 39 | #if ENABLE_FEAT_D128 == 2 |
| 40 | mrs x0, ID_AA64MMFR3_EL1 |
| 41 | tst x0, #(ID_AA64MMFR3_EL1_D128_MASK << ID_AA64MMFR3_EL1_D128_SHIFT) |
| 42 | bne 1f |
| 43 | /* If FEAT_D128 is not implemented then use mrs */ |
| 44 | .inst 0xD5300000 | (\regins) |
| 45 | ret |
| 46 | #endif |
| 47 | 1: |
| 48 | .inst 0xD5700000 | (\regins) |
| 49 | ret |
| 50 | .endm |
| 51 | |
| 52 | /* |
| 53 | * _msrr - Move two adjacent general-purpose registers to System register. |
| 54 | * Instruction: MSRR (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>), <Xt>, <Xt+1> |
| 55 | * |
| 56 | * Arguments/Opcode bit field: |
| 57 | * regins: System register opcode. |
| 58 | * |
| 59 | * Clobbers: x0,x1,x2 |
| 60 | */ |
| 61 | .macro _msrr regins:req |
| 62 | /* If FEAT_D128 is not implemented use msr, dont tamper |
| 63 | * x0, x1 as they maybe used for mrrs */ |
| 64 | #if ENABLE_FEAT_D128 == 2 |
| 65 | mrs x2, ID_AA64MMFR3_EL1 |
| 66 | tst x2, #(ID_AA64MMFR3_EL1_D128_MASK << ID_AA64MMFR3_EL1_D128_SHIFT) |
| 67 | bne 1f |
| 68 | /* If FEAT_D128 is not implemented then use msr */ |
| 69 | .inst 0xD5100000 | (\regins) |
| 70 | ret |
| 71 | #endif |
| 72 | 1: |
| 73 | .inst 0xD5500000 | (\regins) |
| 74 | ret |
| 75 | .endm |
| 76 | |
| 77 | func read_par_el1 |
| 78 | _mrrs 0x87400 /* S3_0_C7_C4_0 */ |
| 79 | endfunc read_par_el1 |
| 80 | |
| 81 | func write_par_el1 |
| 82 | _msrr 0x87400 |
| 83 | endfunc write_par_el1 |
| 84 | |
| 85 | func read_ttbr0_el1 |
| 86 | _mrrs 0x82000 /* S3_0_C2_C0_0 */ |
| 87 | endfunc read_ttbr0_el1 |
| 88 | |
| 89 | func write_ttbr0_el1 |
| 90 | _msrr 0x82000 |
| 91 | endfunc write_ttbr0_el1 |
| 92 | |
| 93 | func read_ttbr1_el1 |
| 94 | _mrrs 0x82020 /* S3_0_C2_C0_1 */ |
| 95 | endfunc read_ttbr1_el1 |
| 96 | |
| 97 | func write_ttbr1_el1 |
| 98 | _msrr 0x82020 |
| 99 | endfunc write_ttbr1_el1 |
| 100 | |
| 101 | func read_ttbr0_el2 |
| 102 | _mrrs 0xC2000 /* S3_4_C2_C0_0 */ |
| 103 | endfunc read_ttbr0_el2 |
| 104 | |
| 105 | func write_ttbr0_el2 |
| 106 | _msrr 0xC2000 |
| 107 | endfunc write_ttbr0_el2 |
| 108 | |
| 109 | func read_ttbr1_el2 |
| 110 | _mrrs 0xC2020 /* S3_4_C2_C0_1 */ |
| 111 | endfunc read_ttbr1_el2 |
| 112 | |
| 113 | func write_ttbr1_el2 |
| 114 | _msrr 0xC2020 |
| 115 | endfunc write_ttbr1_el2 |
| 116 | |
| 117 | func read_vttbr_el2 |
| 118 | _mrrs 0xC2100 /* S3_4_C2_C1_0 */ |
| 119 | endfunc read_vttbr_el2 |
| 120 | |
| 121 | func write_vttbr_el2 |
| 122 | _msrr 0xC2100 |
| 123 | endfunc write_vttbr_el2 |
| 124 | |
| 125 | func read_rcwmask_el1 |
| 126 | _mrrs 0x8D0C0 /* S3_0_C13_C0_6 */ |
| 127 | endfunc read_rcwmask_el1 |
| 128 | |
| 129 | func write_rcwmask_el1 |
| 130 | _msrr 0x8D0C0 |
| 131 | endfunc write_rcwmask_el1 |
| 132 | |
| 133 | func read_rcwsmask_el1 |
| 134 | _mrrs 0x8D060 /* S3_0_C13_C0_3 */ |
| 135 | endfunc read_rcwsmask_el1 |
| 136 | |
| 137 | func write_rcwsmask_el1 |
| 138 | _msrr 0x8D060 |
| 139 | endfunc write_rcwsmask_el1 |