blob: 1fcd13dd0a6b3ff0554381e94359714606329c3d [file] [log] [blame]
Nicolas Le Bayon77e614b2021-05-18 09:11:42 +02001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
4 */
5
6&ddr{
7 st,mem-name = DDR_MEM_NAME;
8 st,mem-speed = <DDR_MEM_SPEED>;
9 st,mem-size = <(DDR_MEM_SIZE >> 32) (DDR_MEM_SIZE & 0xFFFFFFFF)>;
10
11 st,ctl-reg = <
12 DDR_MSTR
13 DDR_MRCTRL0
14 DDR_MRCTRL1
15 DDR_MRCTRL2
16 DDR_DERATEEN
17 DDR_DERATEINT
18 DDR_DERATECTL
19 DDR_PWRCTL
20 DDR_PWRTMG
21 DDR_HWLPCTL
22 DDR_RFSHCTL0
23 DDR_RFSHCTL1
24 DDR_RFSHCTL3
25 DDR_CRCPARCTL0
26 DDR_CRCPARCTL1
27 DDR_INIT0
28 DDR_INIT1
29 DDR_INIT2
30 DDR_INIT3
31 DDR_INIT4
32 DDR_INIT5
33 DDR_INIT6
34 DDR_INIT7
35 DDR_DIMMCTL
36 DDR_RANKCTL
37 DDR_RANKCTL1
38 DDR_ZQCTL0
39 DDR_ZQCTL1
40 DDR_ZQCTL2
41 DDR_DFITMG0
42 DDR_DFITMG1
43 DDR_DFILPCFG0
44 DDR_DFILPCFG1
45 DDR_DFIUPD0
46 DDR_DFIUPD1
47 DDR_DFIUPD2
48 DDR_DFIMISC
49 DDR_DFITMG2
50 DDR_DFITMG3
51 DDR_DBICTL
52 DDR_DFIPHYMSTR
53 DDR_DBG0
54 DDR_DBG1
55 DDR_DBGCMD
56 DDR_SWCTL
57 DDR_SWCTLSTATIC
58 DDR_POISONCFG
59 DDR_PCCFG
60 >;
61
62 st,ctl-timing = <
63 DDR_RFSHTMG
64 DDR_RFSHTMG1
65 DDR_DRAMTMG0
66 DDR_DRAMTMG1
67 DDR_DRAMTMG2
68 DDR_DRAMTMG3
69 DDR_DRAMTMG4
70 DDR_DRAMTMG5
71 DDR_DRAMTMG6
72 DDR_DRAMTMG7
73 DDR_DRAMTMG8
74 DDR_DRAMTMG9
75 DDR_DRAMTMG10
76 DDR_DRAMTMG11
77 DDR_DRAMTMG12
78 DDR_DRAMTMG13
79 DDR_DRAMTMG14
80 DDR_DRAMTMG15
81 DDR_ODTCFG
82 DDR_ODTMAP
83 >;
84
85 st,ctl-map = <
86 DDR_ADDRMAP0
87 DDR_ADDRMAP1
88 DDR_ADDRMAP2
89 DDR_ADDRMAP3
90 DDR_ADDRMAP4
91 DDR_ADDRMAP5
92 DDR_ADDRMAP6
93 DDR_ADDRMAP7
94 DDR_ADDRMAP8
95 DDR_ADDRMAP9
96 DDR_ADDRMAP10
97 DDR_ADDRMAP11
98 >;
99
100 st,ctl-perf = <
101 DDR_SCHED
102 DDR_SCHED1
103 DDR_PERFHPR1
104 DDR_PERFLPR1
105 DDR_PERFWR1
106 DDR_SCHED3
107 DDR_SCHED4
108 DDR_PCFGR_0
109 DDR_PCFGW_0
110 DDR_PCTRL_0
111 DDR_PCFGQOS0_0
112 DDR_PCFGQOS1_0
113 DDR_PCFGWQOS0_0
114 DDR_PCFGWQOS1_0
115 DDR_PCFGR_1
116 DDR_PCFGW_1
117 DDR_PCTRL_1
118 DDR_PCFGQOS0_1
119 DDR_PCFGQOS1_1
120 DDR_PCFGWQOS0_1
121 DDR_PCFGWQOS1_1
122 >;
123
124 st,phy-basic = <
125 DDR_UIB_DRAMTYPE
126 DDR_UIB_DIMMTYPE
127 DDR_UIB_LP4XMODE
128 DDR_UIB_NUMDBYTE
129 DDR_UIB_NUMACTIVEDBYTEDFI0
130 DDR_UIB_NUMACTIVEDBYTEDFI1
131 DDR_UIB_NUMANIB
132 DDR_UIB_NUMRANK_DFI0
133 DDR_UIB_NUMRANK_DFI1
134 DDR_UIB_DRAMDATAWIDTH
135 DDR_UIB_NUMPSTATES
136 DDR_UIB_FREQUENCY_0
137 DDR_UIB_PLLBYPASS_0
138 DDR_UIB_DFIFREQRATIO_0
139 DDR_UIB_DFI1EXISTS
140 DDR_UIB_TRAIN2D
141 DDR_UIB_HARDMACROVER
142 DDR_UIB_READDBIENABLE_0
143 DDR_UIB_DFIMODE
144 >;
145
146 st,phy-advanced = <
147 DDR_UIA_LP4RXPREAMBLEMODE_0
148 DDR_UIA_LP4POSTAMBLEEXT_0
149 DDR_UIA_D4RXPREAMBLELENGTH_0
150 DDR_UIA_D4TXPREAMBLELENGTH_0
151 DDR_UIA_EXTCALRESVAL
152 DDR_UIA_IS2TTIMING_0
153 DDR_UIA_ODTIMPEDANCE_0
154 DDR_UIA_TXIMPEDANCE_0
155 DDR_UIA_ATXIMPEDANCE
156 DDR_UIA_MEMALERTEN
157 DDR_UIA_MEMALERTPUIMP
158 DDR_UIA_MEMALERTVREFLEVEL
159 DDR_UIA_MEMALERTSYNCBYPASS
160 DDR_UIA_DISDYNADRTRI_0
161 DDR_UIA_PHYMSTRTRAININTERVAL_0
162 DDR_UIA_PHYMSTRMAXREQTOACK_0
163 DDR_UIA_WDQSEXT
164 DDR_UIA_CALINTERVAL
165 DDR_UIA_CALONCE
166 DDR_UIA_LP4RL_0
167 DDR_UIA_LP4WL_0
168 DDR_UIA_LP4WLS_0
169 DDR_UIA_LP4DBIRD_0
170 DDR_UIA_LP4DBIWR_0
171 DDR_UIA_LP4NWR_0
172 DDR_UIA_LP4LOWPOWERDRV
173 DDR_UIA_DRAMBYTESWAP
174 DDR_UIA_RXENBACKOFF
175 DDR_UIA_TRAINSEQUENCECTRL
176 DDR_UIA_SNPSUMCTLOPT
177 DDR_UIA_SNPSUMCTLF0RC5X_0
178 DDR_UIA_TXSLEWRISEDQ_0
179 DDR_UIA_TXSLEWFALLDQ_0
180 DDR_UIA_TXSLEWRISEAC
181 DDR_UIA_TXSLEWFALLAC
182 DDR_UIA_DISABLERETRAINING
183 DDR_UIA_DISABLEPHYUPDATE
184 DDR_UIA_ENABLEHIGHCLKSKEWFIX
185 DDR_UIA_DISABLEUNUSEDADDRLNS
186 DDR_UIA_PHYINITSEQUENCENUM
187 DDR_UIA_ENABLEDFICSPOLARITYFIX
188 DDR_UIA_PHYVREF
189 DDR_UIA_SEQUENCECTRL_0
190 >;
191
192 st,phy-mr = <
193 DDR_UIM_MR0_0
194 DDR_UIM_MR1_0
195 DDR_UIM_MR2_0
196 DDR_UIM_MR3_0
197 DDR_UIM_MR4_0
198 DDR_UIM_MR5_0
199 DDR_UIM_MR6_0
200 DDR_UIM_MR11_0
201 DDR_UIM_MR12_0
202 DDR_UIM_MR13_0
203 DDR_UIM_MR14_0
204 DDR_UIM_MR22_0
205 >;
206
207 st,phy-swizzle = <
208 DDR_UIS_SWIZZLE_0
209 DDR_UIS_SWIZZLE_1
210 DDR_UIS_SWIZZLE_2
211 DDR_UIS_SWIZZLE_3
212 DDR_UIS_SWIZZLE_4
213 DDR_UIS_SWIZZLE_5
214 DDR_UIS_SWIZZLE_6
215 DDR_UIS_SWIZZLE_7
216 DDR_UIS_SWIZZLE_8
217 DDR_UIS_SWIZZLE_9
218 DDR_UIS_SWIZZLE_10
219 DDR_UIS_SWIZZLE_11
220 DDR_UIS_SWIZZLE_12
221 DDR_UIS_SWIZZLE_13
222 DDR_UIS_SWIZZLE_14
223 DDR_UIS_SWIZZLE_15
224 DDR_UIS_SWIZZLE_16
225 DDR_UIS_SWIZZLE_17
226 DDR_UIS_SWIZZLE_18
227 DDR_UIS_SWIZZLE_19
228 DDR_UIS_SWIZZLE_20
229 DDR_UIS_SWIZZLE_21
230 DDR_UIS_SWIZZLE_22
231 DDR_UIS_SWIZZLE_23
232 DDR_UIS_SWIZZLE_24
233 DDR_UIS_SWIZZLE_25
234 DDR_UIS_SWIZZLE_26
235 DDR_UIS_SWIZZLE_27
236 DDR_UIS_SWIZZLE_28
237 DDR_UIS_SWIZZLE_29
238 DDR_UIS_SWIZZLE_30
239 DDR_UIS_SWIZZLE_31
240 DDR_UIS_SWIZZLE_32
241 DDR_UIS_SWIZZLE_33
242 DDR_UIS_SWIZZLE_34
243 DDR_UIS_SWIZZLE_35
244 DDR_UIS_SWIZZLE_36
245 DDR_UIS_SWIZZLE_37
246 DDR_UIS_SWIZZLE_38
247 DDR_UIS_SWIZZLE_39
248 DDR_UIS_SWIZZLE_40
249 DDR_UIS_SWIZZLE_41
250 DDR_UIS_SWIZZLE_42
251 DDR_UIS_SWIZZLE_43
252 >;
253};