| Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <asm_macros.S> |
| 8 | #include <assert_macros.S> |
| 9 | #include <xlat_tables_v2.h> |
| 10 | |
| 11 | .global enable_mmu_direct_el1 |
| 12 | .global enable_mmu_direct_el3 |
| 13 | |
| 14 | /* Macros to read and write to system register for a given EL. */ |
| 15 | .macro _msr reg_name, el, gp_reg |
| 16 | msr \reg_name\()_el\()\el, \gp_reg |
| 17 | .endm |
| 18 | |
| 19 | .macro _mrs gp_reg, reg_name, el |
| 20 | mrs \gp_reg, \reg_name\()_el\()\el |
| 21 | .endm |
| 22 | |
| 23 | .macro define_mmu_enable_func el |
| 24 | func enable_mmu_direct_\()el\el |
| 25 | #if ENABLE_ASSERTIONS |
| 26 | _mrs x1, sctlr, \el |
| 27 | tst x1, #SCTLR_M_BIT |
| 28 | ASM_ASSERT(eq) |
| 29 | #endif |
| 30 | |
| 31 | /* Invalidate TLB entries */ |
| 32 | .if \el == 1 |
| 33 | TLB_INVALIDATE(vmalle1) |
| 34 | .else |
| 35 | .if \el == 3 |
| 36 | TLB_INVALIDATE(alle3) |
| 37 | .else |
| 38 | .error "EL must be 1 or 3" |
| 39 | .endif |
| 40 | .endif |
| 41 | |
| 42 | mov x7, x0 |
| 43 | ldr x0, =mmu_cfg_params |
| 44 | |
| 45 | /* MAIR */ |
| 46 | ldr w1, [x0, #(MMU_CFG_MAIR0 << 2)] |
| 47 | _msr mair, \el, x1 |
| 48 | |
| 49 | /* TCR */ |
| 50 | ldr w2, [x0, #(MMU_CFG_TCR << 2)] |
| 51 | _msr tcr, \el, x2 |
| 52 | |
| 53 | /* TTBR */ |
| 54 | ldr w3, [x0, #(MMU_CFG_TTBR0_LO << 2)] |
| 55 | ldr w4, [x0, #(MMU_CFG_TTBR0_HI << 2)] |
| 56 | orr x3, x3, x4, lsl #32 |
| 57 | _msr ttbr0, \el, x3 |
| 58 | |
| 59 | /* |
| 60 | * Ensure all translation table writes have drained into memory, the TLB |
| 61 | * invalidation is complete, and translation register writes are |
| 62 | * committed before enabling the MMU |
| 63 | */ |
| 64 | dsb ish |
| 65 | isb |
| 66 | |
| 67 | /* Set and clear required fields of SCTLR */ |
| 68 | _mrs x4, sctlr, \el |
| 69 | mov_imm x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT |
| 70 | orr x4, x4, x5 |
| 71 | |
| 72 | /* Additionally, amend SCTLR fields based on flags */ |
| 73 | bic x5, x4, #SCTLR_C_BIT |
| 74 | tst x7, #DISABLE_DCACHE |
| 75 | csel x4, x5, x4, ne |
| 76 | |
| 77 | _msr sctlr, \el, x4 |
| 78 | isb |
| 79 | |
| 80 | ret |
| 81 | endfunc enable_mmu_direct_\()el\el |
| 82 | .endm |
| 83 | |
| 84 | /* |
| 85 | * Define MMU-enabling functions for EL1 and EL3: |
| 86 | * |
| 87 | * enable_mmu_direct_el1 |
| 88 | * enable_mmu_direct_el3 |
| 89 | */ |
| 90 | define_mmu_enable_func 1 |
| 91 | define_mmu_enable_func 3 |