Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame^] | 2 | * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 32 | #include <asm_macros.S> |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame^] | 33 | #include <el3_common_macros.S> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 34 | #include <psci.h> |
Achin Gupta | e1aa516 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 35 | #include <xlat_tables.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 36 | |
| 37 | .globl psci_aff_on_finish_entry |
| 38 | .globl psci_aff_suspend_finish_entry |
Achin Gupta | 42c5280 | 2014-05-09 19:32:25 +0100 | [diff] [blame] | 39 | .globl psci_power_down_wfi |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 40 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 41 | /* ----------------------------------------------------- |
| 42 | * This cpu has been physically powered up. Depending |
| 43 | * upon whether it was resumed from suspend or simply |
| 44 | * turned on, call the common power on finisher with |
| 45 | * the handlers (chosen depending upon original state). |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 46 | * ----------------------------------------------------- |
| 47 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 48 | func psci_aff_on_finish_entry |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 49 | adr x23, psci_afflvl_on_finishers |
| 50 | b psci_aff_common_finish_entry |
| 51 | |
| 52 | psci_aff_suspend_finish_entry: |
| 53 | adr x23, psci_afflvl_suspend_finishers |
| 54 | |
| 55 | psci_aff_common_finish_entry: |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame^] | 56 | /* |
| 57 | * On the warm boot path, most of the EL3 initialisations performed by |
| 58 | * 'el3_entrypoint_common' must be skipped: |
| 59 | * |
| 60 | * - No need to determine the type of boot, we know it is a warm boot. |
| 61 | * |
| 62 | * - Do not try to distinguish between primary and secondary CPUs, this |
| 63 | * notion only exists for a cold boot. |
| 64 | * |
| 65 | * - No need to initialise the memory or the C runtime environment, |
| 66 | * it has been done once and for all on the cold boot path. |
Achin Gupta | e1aa516 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 67 | */ |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame^] | 68 | el3_entrypoint_common \ |
| 69 | _set_endian=0 \ |
| 70 | _warm_boot_mailbox=0 \ |
| 71 | _secondary_cold_boot=0 \ |
| 72 | _init_memory=0 \ |
| 73 | _init_c_runtime=0 \ |
| 74 | _exception_vectors=runtime_exceptions |
Achin Gupta | e1aa516 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 75 | |
| 76 | /* -------------------------------------------- |
| 77 | * Enable the MMU with the DCache disabled. It |
| 78 | * is safe to use stacks allocated in normal |
| 79 | * memory as a result. All memory accesses are |
| 80 | * marked nGnRnE when the MMU is disabled. So |
| 81 | * all the stack writes will make it to memory. |
| 82 | * All memory accesses are marked Non-cacheable |
| 83 | * when the MMU is enabled but D$ is disabled. |
| 84 | * So used stack memory is guaranteed to be |
| 85 | * visible immediately after the MMU is enabled |
| 86 | * Enabling the DCache at the same time as the |
| 87 | * MMU can lead to speculatively fetched and |
| 88 | * possibly stale stack memory being read from |
| 89 | * other caches. This can lead to coherency |
| 90 | * issues. |
| 91 | * -------------------------------------------- |
| 92 | */ |
| 93 | mov x0, #DISABLE_DCACHE |
| 94 | bl bl31_plat_enable_mmu |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 95 | |
| 96 | /* --------------------------------------------- |
| 97 | * Call the finishers starting from affinity |
| 98 | * level 0. |
| 99 | * --------------------------------------------- |
| 100 | */ |
Achin Gupta | a45e397 | 2013-12-05 15:10:48 +0000 | [diff] [blame] | 101 | bl get_power_on_target_afflvl |
Andrew Thoelke | 2bc0785 | 2014-06-09 12:44:21 +0100 | [diff] [blame] | 102 | mov x2, x23 |
| 103 | mov x1, x0 |
| 104 | mov x0, #MPIDR_AFFLVL0 |
| 105 | bl psci_afflvl_power_on_finish |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 106 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 107 | b el3_exit |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 108 | endfunc psci_aff_on_finish_entry |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 109 | |
Achin Gupta | 42c5280 | 2014-05-09 19:32:25 +0100 | [diff] [blame] | 110 | /* -------------------------------------------- |
| 111 | * This function is called to indicate to the |
| 112 | * power controller that it is safe to power |
| 113 | * down this cpu. It should not exit the wfi |
| 114 | * and will be released from reset upon power |
| 115 | * up. 'wfi_spill' is used to catch erroneous |
| 116 | * exits from wfi. |
| 117 | * -------------------------------------------- |
| 118 | */ |
| 119 | func psci_power_down_wfi |
Andrew Thoelke | 42e75a7 | 2014-04-28 12:28:39 +0100 | [diff] [blame] | 120 | dsb sy // ensure write buffer empty |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 121 | wfi |
| 122 | wfi_spill: |
| 123 | b wfi_spill |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 124 | endfunc psci_power_down_wfi |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 125 | |