blob: 468688538df0c6b44c1243c8adecc8b2df5c977b [file] [log] [blame]
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +00001/*
Carlo Caione1afdfb02019-08-24 18:47:06 +01002 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
Carlo Caione41f0ed32019-09-03 12:38:58 +01008#include <bl31/interrupt_mgmt.h>
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +00009#include <common/bl_common.h>
10#include <common/debug.h>
11#include <common/ep_info.h>
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000012#include <lib/mmio.h>
Carlo Caione41f0ed32019-09-03 12:38:58 +010013#include <lib/xlat_tables/xlat_tables_v2.h>
14#include <meson_console.h>
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000015#include <platform_def.h>
16#include <stdint.h>
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000017
18/*******************************************************************************
19 * Platform memory map regions
20 ******************************************************************************/
Carlo Caione1e3e33b2019-08-28 15:32:22 +010021#define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
22 AML_NSDRAM0_SIZE, \
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000023 MT_MEMORY | MT_RW | MT_NS)
24
Carlo Caione1e3e33b2019-08-28 15:32:22 +010025#define MAP_NSDRAM1 MAP_REGION_FLAT(AML_NSDRAM1_BASE, \
26 AML_NSDRAM1_SIZE, \
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000027 MT_MEMORY | MT_RW | MT_NS)
28
Carlo Caione1e3e33b2019-08-28 15:32:22 +010029#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
30 AML_SEC_DEVICE0_SIZE, \
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000031 MT_DEVICE | MT_RW | MT_SECURE)
32
Carlo Caione1e3e33b2019-08-28 15:32:22 +010033#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
34 AML_SEC_DEVICE1_SIZE, \
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000035 MT_DEVICE | MT_RW | MT_SECURE)
36
Carlo Caione41f0ed32019-09-03 12:38:58 +010037#define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
38 AML_TZRAM_SIZE, \
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000039 MT_DEVICE | MT_RW | MT_SECURE)
40
Carlo Caione1e3e33b2019-08-28 15:32:22 +010041#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
42 AML_SEC_DEVICE2_SIZE, \
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000043 MT_DEVICE | MT_RW | MT_SECURE)
44
Carlo Caione1e3e33b2019-08-28 15:32:22 +010045#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE, \
46 AML_SEC_DEVICE3_SIZE, \
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000047 MT_DEVICE | MT_RW | MT_SECURE)
48
Carlo Caione1e3e33b2019-08-28 15:32:22 +010049static const mmap_region_t gxl_mmap[] = {
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000050 MAP_NSDRAM0,
51 MAP_NSDRAM1,
52 MAP_SEC_DEVICE0,
53 MAP_SEC_DEVICE1,
54 MAP_TZRAM,
55 MAP_SEC_DEVICE2,
56 MAP_SEC_DEVICE3,
57 {0}
58};
59
60/*******************************************************************************
61 * Per-image regions
62 ******************************************************************************/
63#define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \
64 BL31_END - BL31_BASE, \
65 MT_MEMORY | MT_RW | MT_SECURE)
66
67#define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \
68 BL_CODE_END - BL_CODE_BASE, \
69 MT_CODE | MT_SECURE)
70
71#define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \
72 BL_RO_DATA_END - BL_RO_DATA_BASE, \
73 MT_RO_DATA | MT_SECURE)
74
75#define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, \
76 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
77 MT_DEVICE | MT_RW | MT_SECURE)
78
79/*******************************************************************************
80 * Function that sets up the translation tables.
81 ******************************************************************************/
Carlo Caionebf2d6262019-08-25 18:09:03 +010082void aml_setup_page_tables(void)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000083{
84#if IMAGE_BL31
Carlo Caione1e3e33b2019-08-28 15:32:22 +010085 const mmap_region_t gxl_bl_mmap[] = {
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000086 MAP_BL31,
87 MAP_BL_CODE,
88 MAP_BL_RO_DATA,
89#if USE_COHERENT_MEM
90 MAP_BL_COHERENT,
91#endif
92 {0}
93 };
94#endif
95
Carlo Caione1e3e33b2019-08-28 15:32:22 +010096 mmap_add(gxl_bl_mmap);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000097
Carlo Caione1e3e33b2019-08-28 15:32:22 +010098 mmap_add(gxl_mmap);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000099
100 init_xlat_tables();
101}
102
103/*******************************************************************************
104 * Function that sets up the console
105 ******************************************************************************/
Carlo Caione1e3e33b2019-08-28 15:32:22 +0100106static console_meson_t gxl_console;
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000107
Carlo Caionebf2d6262019-08-25 18:09:03 +0100108void aml_console_init(void)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000109{
Carlo Caione1afdfb02019-08-24 18:47:06 +0100110 int rc = console_meson_register(AML_UART0_AO_BASE,
111 AML_UART0_AO_CLK_IN_HZ,
112 AML_UART_BAUDRATE,
Carlo Caione1e3e33b2019-08-28 15:32:22 +0100113 &gxl_console);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000114 if (rc == 0) {
115 /*
116 * The crash console doesn't use the multi console API, it uses
117 * the core console functions directly. It is safe to call panic
118 * and let it print debug information.
119 */
120 panic();
121 }
122
Carlo Caione1e3e33b2019-08-28 15:32:22 +0100123 console_set_scope(&gxl_console.console,
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000124 CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME);
125}
126
127/*******************************************************************************
128 * Function that returns the system counter frequency
129 ******************************************************************************/
130unsigned int plat_get_syscnt_freq2(void)
131{
132 uint32_t val;
133
Carlo Caione1e3e33b2019-08-28 15:32:22 +0100134 val = mmio_read_32(AML_SYS_CPU_CFG7);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000135 val &= 0xFDFFFFFF;
Carlo Caione1e3e33b2019-08-28 15:32:22 +0100136 mmio_write_32(AML_SYS_CPU_CFG7, val);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000137
Carlo Caione1e3e33b2019-08-28 15:32:22 +0100138 val = mmio_read_32(AML_AO_TIMESTAMP_CNTL);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000139 val &= 0xFFFFFE00;
Carlo Caione1e3e33b2019-08-28 15:32:22 +0100140 mmio_write_32(AML_AO_TIMESTAMP_CNTL, val);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000141
Carlo Caione1e3e33b2019-08-28 15:32:22 +0100142 return AML_OSC24M_CLK_IN_HZ;
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000143}