blob: 7703cbe553679c574c27a6052ef5c55de7935fae [file] [log] [blame]
Soby Mathewe063d3c2015-10-07 09:45:27 +01001/*
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +01002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Soby Mathewe063d3c2015-10-07 09:45:27 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewe063d3c2015-10-07 09:45:27 +01005 */
6
7#ifndef __GICV2_PRIVATE_H__
8#define __GICV2_PRIVATE_H__
9
10#include <gicv2.h>
11#include <mmio.h>
12#include <stdint.h>
13
14/*******************************************************************************
15 * Private function prototypes
16 ******************************************************************************/
17void gicv2_spis_configure_defaults(uintptr_t gicd_base);
18void gicv2_secure_spis_configure(uintptr_t gicd_base,
19 unsigned int num_ints,
20 const unsigned int *sec_intr_list);
21void gicv2_secure_ppi_sgi_setup(uintptr_t gicd_base,
22 unsigned int num_ints,
23 const unsigned int *sec_intr_list);
24unsigned int gicv2_get_cpuif_id(uintptr_t base);
25
26/*******************************************************************************
27 * GIC Distributor interface accessors for reading entire registers
28 ******************************************************************************/
29static inline unsigned int gicd_read_pidr2(uintptr_t base)
30{
31 return mmio_read_32(base + GICD_PIDR2_GICV2);
32}
33
34/*******************************************************************************
35 * GIC CPU interface accessors for reading entire registers
36 ******************************************************************************/
37
38static inline unsigned int gicc_read_ctlr(uintptr_t base)
39{
40 return mmio_read_32(base + GICC_CTLR);
41}
42
43static inline unsigned int gicc_read_pmr(uintptr_t base)
44{
45 return mmio_read_32(base + GICC_PMR);
46}
47
48static inline unsigned int gicc_read_BPR(uintptr_t base)
49{
50 return mmio_read_32(base + GICC_BPR);
51}
52
53static inline unsigned int gicc_read_IAR(uintptr_t base)
54{
55 return mmio_read_32(base + GICC_IAR);
56}
57
58static inline unsigned int gicc_read_EOIR(uintptr_t base)
59{
60 return mmio_read_32(base + GICC_EOIR);
61}
62
63static inline unsigned int gicc_read_hppir(uintptr_t base)
64{
65 return mmio_read_32(base + GICC_HPPIR);
66}
67
68static inline unsigned int gicc_read_ahppir(uintptr_t base)
69{
70 return mmio_read_32(base + GICC_AHPPIR);
71}
72
73static inline unsigned int gicc_read_dir(uintptr_t base)
74{
75 return mmio_read_32(base + GICC_DIR);
76}
77
78static inline unsigned int gicc_read_iidr(uintptr_t base)
79{
80 return mmio_read_32(base + GICC_IIDR);
81}
82
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +010083static inline unsigned int gicc_read_rpr(uintptr_t base)
84{
85 return mmio_read_32(base + GICC_RPR);
86}
87
Soby Mathewe063d3c2015-10-07 09:45:27 +010088/*******************************************************************************
89 * GIC CPU interface accessors for writing entire registers
90 ******************************************************************************/
91
92static inline void gicc_write_ctlr(uintptr_t base, unsigned int val)
93{
94 mmio_write_32(base + GICC_CTLR, val);
95}
96
97static inline void gicc_write_pmr(uintptr_t base, unsigned int val)
98{
99 mmio_write_32(base + GICC_PMR, val);
100}
101
102static inline void gicc_write_BPR(uintptr_t base, unsigned int val)
103{
104 mmio_write_32(base + GICC_BPR, val);
105}
106
107
108static inline void gicc_write_IAR(uintptr_t base, unsigned int val)
109{
110 mmio_write_32(base + GICC_IAR, val);
111}
112
113static inline void gicc_write_EOIR(uintptr_t base, unsigned int val)
114{
115 mmio_write_32(base + GICC_EOIR, val);
116}
117
118static inline void gicc_write_hppir(uintptr_t base, unsigned int val)
119{
120 mmio_write_32(base + GICC_HPPIR, val);
121}
122
123static inline void gicc_write_dir(uintptr_t base, unsigned int val)
124{
125 mmio_write_32(base + GICC_DIR, val);
126}
127
128#endif /* __GICV2_PRIVATE_H__ */