blob: f4781484c9c0ed3c669c7854f4061c0a434226ad [file] [log] [blame]
Dimitris Papastamos446f7f12017-11-30 14:53:53 +00001/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <context.h>
10
11 .globl workaround_mmu_runtime_exceptions
12
13vector_base workaround_mmu_runtime_exceptions
14
15 .macro apply_workaround
16 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
17 mrs x0, sctlr_el3
18 /* Disable MMU */
19 bic x1, x0, #SCTLR_M_BIT
20 msr sctlr_el3, x1
21 isb
22 /* Restore MMU config */
23 msr sctlr_el3, x0
24 isb
25 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
26 .endm
27
28 /* ---------------------------------------------------------------------
29 * Current EL with SP_EL0 : 0x0 - 0x200
30 * ---------------------------------------------------------------------
31 */
32vector_entry workaround_mmu_sync_exception_sp_el0
33 b sync_exception_sp_el0
34 check_vector_size workaround_mmu_sync_exception_sp_el0
35
36vector_entry workaround_mmu_irq_sp_el0
37 b irq_sp_el0
38 check_vector_size workaround_mmu_irq_sp_el0
39
40vector_entry workaround_mmu_fiq_sp_el0
41 b fiq_sp_el0
42 check_vector_size workaround_mmu_fiq_sp_el0
43
44vector_entry workaround_mmu_serror_sp_el0
45 b serror_sp_el0
46 check_vector_size workaround_mmu_serror_sp_el0
47
48 /* ---------------------------------------------------------------------
49 * Current EL with SP_ELx: 0x200 - 0x400
50 * ---------------------------------------------------------------------
51 */
52vector_entry workaround_mmu_sync_exception_sp_elx
53 b sync_exception_sp_elx
54 check_vector_size workaround_mmu_sync_exception_sp_elx
55
56vector_entry workaround_mmu_irq_sp_elx
57 b irq_sp_elx
58 check_vector_size workaround_mmu_irq_sp_elx
59
60vector_entry workaround_mmu_fiq_sp_elx
61 b fiq_sp_elx
62 check_vector_size workaround_mmu_fiq_sp_elx
63
64vector_entry workaround_mmu_serror_sp_elx
65 b serror_sp_elx
66 check_vector_size workaround_mmu_serror_sp_elx
67
68 /* ---------------------------------------------------------------------
69 * Lower EL using AArch64 : 0x400 - 0x600
70 * ---------------------------------------------------------------------
71 */
72vector_entry workaround_mmu_sync_exception_aarch64
73 apply_workaround
74 b sync_exception_aarch64
75 check_vector_size workaround_mmu_sync_exception_aarch64
76
77vector_entry workaround_mmu_irq_aarch64
78 apply_workaround
79 b irq_aarch64
80 check_vector_size workaround_mmu_irq_aarch64
81
82vector_entry workaround_mmu_fiq_aarch64
83 apply_workaround
84 b fiq_aarch64
85 check_vector_size workaround_mmu_fiq_aarch64
86
87vector_entry workaround_mmu_serror_aarch64
88 apply_workaround
89 b serror_aarch64
90 check_vector_size workaround_mmu_serror_aarch64
91
92 /* ---------------------------------------------------------------------
93 * Lower EL using AArch32 : 0x600 - 0x800
94 * ---------------------------------------------------------------------
95 */
96vector_entry workaround_mmu_sync_exception_aarch32
97 apply_workaround
98 b sync_exception_aarch32
99 check_vector_size workaround_mmu_sync_exception_aarch32
100
101vector_entry workaround_mmu_irq_aarch32
102 apply_workaround
103 b irq_aarch32
104 check_vector_size workaround_mmu_irq_aarch32
105
106vector_entry workaround_mmu_fiq_aarch32
107 apply_workaround
108 b fiq_aarch32
109 check_vector_size workaround_mmu_fiq_aarch32
110
111vector_entry workaround_mmu_serror_aarch32
112 apply_workaround
113 b serror_aarch32
114 check_vector_size workaround_mmu_serror_aarch32