Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | #include <lib/xlat_tables/xlat_tables_defs.h> |
| 12 | #include <plat/arm/board/common/board_css_def.h> |
| 13 | #include <plat/arm/board/common/v2m_def.h> |
| 14 | #include <plat/arm/common/arm_def.h> |
| 15 | #include <plat/arm/common/arm_spm_def.h> |
| 16 | #include <plat/arm/css/common/css_def.h> |
| 17 | #include <plat/arm/soc/common/soc_css_def.h> |
| 18 | #include <plat/common/common_def.h> |
| 19 | |
| 20 | #define PLATFORM_CORE_COUNT 4 |
| 21 | |
| 22 | #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ |
| 23 | |
| 24 | /* |
| 25 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 26 | * plat_arm_mmap array defined for each BL stage. |
| 27 | */ |
| 28 | #if defined(IMAGE_BL31) |
| 29 | # if SPM_MM |
| 30 | # define PLAT_ARM_MMAP_ENTRIES 9 |
| 31 | # define MAX_XLAT_TABLES 7 |
| 32 | # define PLAT_SP_IMAGE_MMAP_REGIONS 7 |
| 33 | # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 |
| 34 | # else |
| 35 | # define PLAT_ARM_MMAP_ENTRIES 8 |
| 36 | # define MAX_XLAT_TABLES 8 |
| 37 | # endif |
| 38 | #elif defined(IMAGE_BL32) |
| 39 | # define PLAT_ARM_MMAP_ENTRIES 8 |
| 40 | # define MAX_XLAT_TABLES 5 |
| 41 | #elif !USE_ROMLIB |
| 42 | # define PLAT_ARM_MMAP_ENTRIES 11 |
| 43 | # define MAX_XLAT_TABLES 7 |
| 44 | #else |
| 45 | # define PLAT_ARM_MMAP_ENTRIES 12 |
| 46 | # define MAX_XLAT_TABLES 6 |
| 47 | #endif |
| 48 | |
| 49 | /* |
| 50 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 51 | * plus a little space for growth. |
| 52 | */ |
| 53 | #define PLAT_ARM_MAX_BL1_RW_SIZE 0xC000 |
| 54 | |
| 55 | /* |
| 56 | * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page |
| 57 | */ |
| 58 | |
| 59 | #if USE_ROMLIB |
| 60 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 |
| 61 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 |
| 62 | #else |
| 63 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 |
| 64 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 |
| 65 | #endif |
| 66 | |
| 67 | /* |
| 68 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 69 | * little space for growth. |
| 70 | */ |
| 71 | #if TRUSTED_BOARD_BOOT |
| 72 | # define PLAT_ARM_MAX_BL2_SIZE 0x1E000 |
| 73 | #else |
| 74 | # define PLAT_ARM_MAX_BL2_SIZE 0x11000 |
| 75 | #endif |
| 76 | |
| 77 | /* |
| 78 | * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is |
| 79 | * calculated using the current BL31 PROGBITS debug size plus the sizes of |
| 80 | * BL2 and BL1-RW |
| 81 | */ |
| 82 | #define PLAT_ARM_MAX_BL31_SIZE 0x3B000 |
| 83 | |
| 84 | /* |
| 85 | * Size of cacheable stacks |
| 86 | */ |
| 87 | #if defined(IMAGE_BL1) |
| 88 | # if TRUSTED_BOARD_BOOT |
| 89 | # define PLATFORM_STACK_SIZE 0x1000 |
| 90 | # else |
| 91 | # define PLATFORM_STACK_SIZE 0x440 |
| 92 | # endif |
| 93 | #elif defined(IMAGE_BL2) |
| 94 | # if TRUSTED_BOARD_BOOT |
| 95 | # define PLATFORM_STACK_SIZE 0x1000 |
| 96 | # else |
| 97 | # define PLATFORM_STACK_SIZE 0x400 |
| 98 | # endif |
| 99 | #elif defined(IMAGE_BL2U) |
| 100 | # define PLATFORM_STACK_SIZE 0x400 |
| 101 | #elif defined(IMAGE_BL31) |
| 102 | # if SPM_MM |
| 103 | # define PLATFORM_STACK_SIZE 0x500 |
| 104 | # else |
| 105 | # define PLATFORM_STACK_SIZE 0x400 |
| 106 | # endif |
| 107 | #elif defined(IMAGE_BL32) |
| 108 | # define PLATFORM_STACK_SIZE 0x440 |
| 109 | #endif |
| 110 | |
| 111 | |
| 112 | #define TC0_DEVICE_BASE 0x21000000 |
| 113 | #define TC0_DEVICE_SIZE 0x5f000000 |
| 114 | |
| 115 | // TC0_MAP_DEVICE covers different peripherals |
| 116 | // available to the platform |
| 117 | #define TC0_MAP_DEVICE MAP_REGION_FLAT( \ |
| 118 | TC0_DEVICE_BASE, \ |
| 119 | TC0_DEVICE_SIZE, \ |
| 120 | MT_DEVICE | MT_RW | MT_SECURE) |
| 121 | |
| 122 | |
| 123 | #define TC0_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ |
| 124 | V2M_FLASH0_SIZE, \ |
| 125 | MT_DEVICE | MT_RO | MT_SECURE) |
| 126 | |
| 127 | #define PLAT_ARM_NSTIMER_FRAME_ID 0 |
| 128 | |
| 129 | #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 |
| 130 | #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */ |
| 131 | |
| 132 | #define PLAT_ARM_NSRAM_BASE 0x06000000 |
| 133 | #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ |
| 134 | |
| 135 | #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) |
| 136 | #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) |
| 137 | |
| 138 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) |
| 139 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
| 140 | |
| 141 | #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ |
| 142 | PLAT_SP_IMAGE_NS_BUF_SIZE) |
| 143 | |
| 144 | /******************************************************************************* |
| 145 | * Memprotect definitions |
| 146 | ******************************************************************************/ |
| 147 | /* PSCI memory protect definitions: |
| 148 | * This variable is stored in a non-secure flash because some ARM reference |
| 149 | * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT |
| 150 | * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. |
| 151 | */ |
| 152 | #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ |
| 153 | V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) |
| 154 | |
| 155 | /*Secure Watchdog Constants */ |
| 156 | #define SBSA_SECURE_WDOG_BASE UL(0x2A480000) |
| 157 | #define SBSA_SECURE_WDOG_TIMEOUT UL(100) |
| 158 | |
| 159 | #define PLAT_ARM_SCMI_CHANNEL_COUNT 1 |
| 160 | |
| 161 | #define PLAT_ARM_CLUSTER_COUNT U(1) |
| 162 | #define PLAT_MAX_CPUS_PER_CLUSTER U(4) |
| 163 | #define PLAT_MAX_PE_PER_CPU U(1) |
| 164 | |
| 165 | #define PLAT_CSS_MHU_BASE UL(0x45400000) |
| 166 | #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE |
| 167 | |
| 168 | #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 |
| 169 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 |
| 170 | |
| 171 | /* |
| 172 | * Physical and virtual address space limits for MMU in AARCH64 |
| 173 | */ |
| 174 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) |
| 175 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) |
| 176 | |
| 177 | /* GIC related constants */ |
| 178 | #define PLAT_ARM_GICD_BASE UL(0x30000000) |
| 179 | #define PLAT_ARM_GICC_BASE UL(0x2C000000) |
| 180 | #define PLAT_ARM_GICR_BASE UL(0x30140000) |
| 181 | |
| 182 | /* |
| 183 | * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current |
| 184 | * SCP_BL2 size plus a little space for growth. |
| 185 | */ |
Usama Arif | 82d931e | 2020-09-07 18:11:22 +0100 | [diff] [blame] | 186 | #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x20000 |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 187 | |
| 188 | /* |
| 189 | * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current |
| 190 | * SCP_BL2U size plus a little space for growth. |
| 191 | */ |
Usama Arif | 82d931e | 2020-09-07 18:11:22 +0100 | [diff] [blame] | 192 | #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x20000 |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 193 | |
| 194 | #endif /* PLATFORM_DEF_H */ |