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Xing Zheng93280b72016-10-26 21:25:26 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Xing Zheng93280b72016-10-26 21:25:26 +08005 */
6
Xing Zhengb4bcc1d2017-02-24 16:26:11 +08007#include <dram_regs.h>
Xing Zheng93280b72016-10-26 21:25:26 +08008#include <m0_param.h>
Xing Zhengb4bcc1d2017-02-24 16:26:11 +08009#include <pmu_bits.h>
10#include <pmu_regs.h>
11#include "misc_regs.h"
Xing Zheng93280b72016-10-26 21:25:26 +080012#include "rk3399_mcu.h"
13
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080014static uint32_t gatedis_con0;
Lin Huang25103662016-12-30 11:50:01 +080015
Xing Zheng93280b72016-10-26 21:25:26 +080016static void idle_port(void)
17{
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080018 gatedis_con0 = mmio_read_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0);
19 mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, 0x3fffffff);
20
Xing Zheng93280b72016-10-26 21:25:26 +080021 mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ,
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080022 (1 << PMU_IDLE_REQ_MSCH0) | (1 << PMU_IDLE_REQ_MSCH1));
Xing Zheng93280b72016-10-26 21:25:26 +080023 while ((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) &
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080024 ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) !=
25 ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0)))
Xing Zheng93280b72016-10-26 21:25:26 +080026 continue;
27}
28
29static void deidle_port(void)
30{
31 mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ,
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080032 (1 << PMU_IDLE_REQ_MSCH0) | (1 << PMU_IDLE_REQ_MSCH1));
Xing Zheng93280b72016-10-26 21:25:26 +080033 while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) &
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080034 ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0)))
Xing Zheng93280b72016-10-26 21:25:26 +080035 continue;
Lin Huang25103662016-12-30 11:50:01 +080036
37 /* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080038 mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, gatedis_con0);
Xing Zheng93280b72016-10-26 21:25:26 +080039}
40
41static void ddr_set_pll(void)
42{
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080043 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE));
Xing Zheng93280b72016-10-26 21:25:26 +080044
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080045 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(1));
46 mmio_write_32(CRU_BASE + CRU_DPLL_CON0,
Xing Zheng93280b72016-10-26 21:25:26 +080047 mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON0));
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080048 mmio_write_32(CRU_BASE + CRU_DPLL_CON1,
Xing Zheng93280b72016-10-26 21:25:26 +080049 mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON1));
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080050 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(0));
Xing Zheng93280b72016-10-26 21:25:26 +080051
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080052 while ((mmio_read_32(CRU_BASE + CRU_DPLL_CON2) & (1u << 31)) == 0)
Xing Zheng93280b72016-10-26 21:25:26 +080053 continue;
54
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080055 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE));
Xing Zheng93280b72016-10-26 21:25:26 +080056}
57
58void handle_dram(void)
59{
Derek Basehore397046c2017-02-01 18:09:13 -080060 mmio_setbits_32(PHY_REG(0, 927), (1 << 22));
61 mmio_setbits_32(PHY_REG(1, 927), (1 << 22));
Xing Zheng93280b72016-10-26 21:25:26 +080062 idle_port();
63
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080064 mmio_write_32(CIC_BASE + CIC_CTRL0,
Xing Zheng93280b72016-10-26 21:25:26 +080065 (((0x3 << 4) | (1 << 2) | 1) << 16) |
66 (1 << 2) | 1 |
67 mmio_read_32(PARAM_ADDR + PARAM_FREQ_SELECT));
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080068 while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2)) == 0)
Xing Zheng93280b72016-10-26 21:25:26 +080069 continue;
70
71 ddr_set_pll();
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080072 mmio_write_32(CIC_BASE + CIC_CTRL0, 0x20002);
73 while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 0)) == 0)
Xing Zheng93280b72016-10-26 21:25:26 +080074 continue;
75
76 deidle_port();
Derek Basehore397046c2017-02-01 18:09:13 -080077 mmio_clrbits_32(PHY_REG(0, 927), (1 << 22));
78 mmio_clrbits_32(PHY_REG(1, 927), (1 << 22));
Xing Zheng93280b72016-10-26 21:25:26 +080079}