Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <stdint.h> |
| 8 | #include <string.h> |
| 9 | #include <stdio.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | |
| 11 | #include <common/debug.h> |
| 12 | #include <lib/mmio.h> |
| 13 | |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 14 | #include "ddr_regdef.h" |
| 15 | #include "init_dram_tbl_h3.h" |
| 16 | #include "init_dram_tbl_m3.h" |
| 17 | #include "init_dram_tbl_h3ver2.h" |
| 18 | #include "init_dram_tbl_m3n.h" |
| 19 | #include "boot_init_dram_regdef.h" |
| 20 | #include "boot_init_dram.h" |
| 21 | #include "dram_sub_func.h" |
| 22 | #include "micro_delay.h" |
| 23 | |
| 24 | #define DDR_BACKUPMODE |
| 25 | #define FATAL_MSG(x) NOTICE(x) |
| 26 | |
| 27 | /******************************************************************************* |
| 28 | * variables |
| 29 | ******************************************************************************/ |
| 30 | #ifdef RCAR_DDR_FIXED_LSI_TYPE |
| 31 | #ifndef RCAR_AUTO |
| 32 | #define RCAR_AUTO 99 |
| 33 | #define RCAR_H3 0 |
| 34 | #define RCAR_M3 1 |
| 35 | #define RCAR_M3N 2 |
| 36 | #define RCAR_E3 3 /* NON */ |
| 37 | #define RCAR_H3N 4 |
| 38 | |
| 39 | #define RCAR_CUT_10 0 |
| 40 | #define RCAR_CUT_11 1 |
| 41 | #define RCAR_CUT_20 10 |
| 42 | #define RCAR_CUT_30 20 |
| 43 | #endif |
| 44 | #ifndef RCAR_LSI |
| 45 | #define RCAR_LSI RCAR_AUTO |
| 46 | #endif |
| 47 | #if(RCAR_LSI==RCAR_AUTO) |
| 48 | static uint32_t Prr_Product; |
| 49 | static uint32_t Prr_Cut; |
| 50 | #else |
| 51 | #if(RCAR_LSI==RCAR_H3) |
| 52 | static const uint32_t Prr_Product = PRR_PRODUCT_H3; |
| 53 | #elif(RCAR_LSI==RCAR_M3) |
| 54 | static const uint32_t Prr_Product = PRR_PRODUCT_M3; |
| 55 | #elif(RCAR_LSI==RCAR_M3N) |
| 56 | static const uint32_t Prr_Product = PRR_PRODUCT_M3N; |
| 57 | #elif(RCAR_LSI==RCAR_H3N) |
| 58 | static const uint32_t Prr_Product = PRR_PRODUCT_H3; |
| 59 | #endif /* RCAR_LSI */ |
| 60 | |
| 61 | #ifndef RCAR_LSI_CUT |
| 62 | static uint32_t Prr_Cut; |
| 63 | #else /* RCAR_LSI_CUT */ |
| 64 | #if(RCAR_LSI_CUT==RCAR_CUT_10) |
| 65 | static const uint32_t Prr_Cut = PRR_PRODUCT_10; |
| 66 | #elif(RCAR_LSI_CUT==RCAR_CUT_11) |
| 67 | static const uint32_t Prr_Cut = PRR_PRODUCT_11; |
| 68 | #elif(RCAR_LSI_CUT==RCAR_CUT_20) |
| 69 | static const uint32_t Prr_Cut = PRR_PRODUCT_20; |
| 70 | #elif(RCAR_LSI_CUT==RCAR_CUT_30) |
| 71 | static const uint32_t Prr_Cut = PRR_PRODUCT_30; |
| 72 | #endif /* RCAR_LSI_CUT */ |
| 73 | #endif /* RCAR_LSI_CUT */ |
| 74 | #endif /* RCAR_AUTO_NON */ |
| 75 | #else /* RCAR_DDR_FIXED_LSI_TYPE */ |
| 76 | static uint32_t Prr_Product; |
| 77 | static uint32_t Prr_Cut; |
| 78 | #endif /* RCAR_DDR_FIXED_LSI_TYPE */ |
| 79 | |
| 80 | char *pRCAR_DDR_VERSION; |
| 81 | uint32_t _cnf_BOARDTYPE; |
| 82 | static uint32_t *pDDR_REGDEF_TBL; |
| 83 | static uint32_t brd_clk; |
| 84 | static uint32_t brd_clkdiv; |
| 85 | static uint32_t brd_clkdiva; |
| 86 | static uint32_t ddr_mbps; |
| 87 | static uint32_t ddr_mbpsdiv; |
| 88 | static uint32_t ddr_tccd; |
| 89 | static struct _boardcnf *Boardcnf; |
| 90 | uint32_t ddr_phyvalid; |
| 91 | uint32_t ddr_density[DRAM_CH_CNT][CS_CNT]; |
| 92 | static uint32_t ch_have_this_cs[CS_CNT]; |
| 93 | static uint32_t rdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; |
| 94 | static uint32_t rdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; |
| 95 | static uint32_t rdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; |
| 96 | static uint32_t rdqdm_nw[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; |
| 97 | static uint32_t rdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; |
| 98 | static uint32_t rdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2]; |
| 99 | |
| 100 | static uint32_t wdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; |
| 101 | static uint32_t wdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; |
| 102 | static uint32_t wdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; |
| 103 | static uint32_t wdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; |
| 104 | static uint32_t wdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; |
| 105 | static uint32_t max_density; |
| 106 | static uint32_t ddr0800_mul; |
| 107 | static uint32_t ddr_mul; |
| 108 | static uint32_t ddr_mbps; |
| 109 | static uint32_t DDR_PHY_SLICE_REGSET_OFS; |
| 110 | static uint32_t DDR_PHY_ADR_V_REGSET_OFS; |
| 111 | static uint32_t DDR_PHY_ADR_I_REGSET_OFS; |
| 112 | static uint32_t DDR_PHY_ADR_G_REGSET_OFS; |
| 113 | static uint32_t DDR_PI_REGSET_OFS; |
| 114 | static uint32_t DDR_PHY_SLICE_REGSET_SIZE; |
| 115 | static uint32_t DDR_PHY_ADR_V_REGSET_SIZE; |
| 116 | static uint32_t DDR_PHY_ADR_I_REGSET_SIZE; |
| 117 | static uint32_t DDR_PHY_ADR_G_REGSET_SIZE; |
| 118 | static uint32_t DDR_PI_REGSET_SIZE; |
| 119 | static uint32_t DDR_PHY_SLICE_REGSET_NUM; |
| 120 | static uint32_t DDR_PHY_ADR_V_REGSET_NUM; |
| 121 | static uint32_t DDR_PHY_ADR_I_REGSET_NUM; |
| 122 | static uint32_t DDR_PHY_ADR_G_REGSET_NUM; |
| 123 | static uint32_t DDR_PI_REGSET_NUM; |
| 124 | static uint32_t DDR_PHY_ADR_I_NUM; |
| 125 | #define DDR_PHY_REGSET_MAX 128 |
| 126 | #define DDR_PI_REGSET_MAX 320 |
| 127 | static uint32_t _cnf_DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX]; |
| 128 | static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX]; |
| 129 | static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX]; |
| 130 | static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX]; |
| 131 | static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX]; |
| 132 | static uint32_t Pll3Mode; |
| 133 | static uint32_t loop_max; |
| 134 | #ifdef DDR_BACKUPMODE |
| 135 | uint32_t ddrBackup; |
| 136 | /* #define DDR_BACKUPMODE_HALF //for Half channel(ch0,1 only) */ |
| 137 | #endif |
| 138 | |
| 139 | #ifdef ddr_qos_init_setting /* only for non qos_init */ |
| 140 | #define OPERATING_FREQ (400U) /* Mhz */ |
| 141 | #define BASE_SUB_SLOT_NUM (0x6U) |
| 142 | #define SUB_SLOT_CYCLE (0x7EU) /* 126 */ |
| 143 | #define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */ |
| 144 | |
| 145 | uint32_t get_refperiod(void) |
| 146 | { |
| 147 | return QOSWT_WTSET0_CYCLE; |
| 148 | } |
| 149 | #else /* ddr_qos_init_setting // only for non qos_init */ |
| 150 | extern uint32_t get_refperiod(void); |
| 151 | #endif /* ddr_qos_init_setting // only for non qos_init */ |
| 152 | |
| 153 | #define _reg_PHY_RX_CAL_X_NUM 11 |
| 154 | static const uint32_t _reg_PHY_RX_CAL_X[_reg_PHY_RX_CAL_X_NUM] = { |
| 155 | _reg_PHY_RX_CAL_DQ0, |
| 156 | _reg_PHY_RX_CAL_DQ1, |
| 157 | _reg_PHY_RX_CAL_DQ2, |
| 158 | _reg_PHY_RX_CAL_DQ3, |
| 159 | _reg_PHY_RX_CAL_DQ4, |
| 160 | _reg_PHY_RX_CAL_DQ5, |
| 161 | _reg_PHY_RX_CAL_DQ6, |
| 162 | _reg_PHY_RX_CAL_DQ7, |
| 163 | _reg_PHY_RX_CAL_DM, |
| 164 | _reg_PHY_RX_CAL_DQS, |
| 165 | _reg_PHY_RX_CAL_FDBK |
| 166 | }; |
| 167 | |
| 168 | #define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10 |
| 169 | static const uint32_t |
| 170 | _reg_PHY_CLK_WRX_SLAVE_DELAY[_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = { |
| 171 | _reg_PHY_CLK_WRDQ0_SLAVE_DELAY, |
| 172 | _reg_PHY_CLK_WRDQ1_SLAVE_DELAY, |
| 173 | _reg_PHY_CLK_WRDQ2_SLAVE_DELAY, |
| 174 | _reg_PHY_CLK_WRDQ3_SLAVE_DELAY, |
| 175 | _reg_PHY_CLK_WRDQ4_SLAVE_DELAY, |
| 176 | _reg_PHY_CLK_WRDQ5_SLAVE_DELAY, |
| 177 | _reg_PHY_CLK_WRDQ6_SLAVE_DELAY, |
| 178 | _reg_PHY_CLK_WRDQ7_SLAVE_DELAY, |
| 179 | _reg_PHY_CLK_WRDM_SLAVE_DELAY, |
| 180 | _reg_PHY_CLK_WRDQS_SLAVE_DELAY |
| 181 | }; |
| 182 | |
| 183 | #define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9 |
| 184 | static const uint32_t |
| 185 | _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = { |
| 186 | _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY, |
| 187 | _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY, |
| 188 | _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY, |
| 189 | _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY, |
| 190 | _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY, |
| 191 | _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY, |
| 192 | _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY, |
| 193 | _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY, |
| 194 | _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY |
| 195 | }; |
| 196 | |
| 197 | #define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9 |
| 198 | static const uint32_t |
| 199 | _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = { |
| 200 | _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY, |
| 201 | _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY, |
| 202 | _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY, |
| 203 | _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY, |
| 204 | _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY, |
| 205 | _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY, |
| 206 | _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY, |
| 207 | _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY, |
| 208 | _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY |
| 209 | }; |
| 210 | |
| 211 | #define _reg_PHY_PAD_TERM_X_NUM 8 |
| 212 | static const uint32_t _reg_PHY_PAD_TERM_X[_reg_PHY_PAD_TERM_X_NUM] = { |
| 213 | _reg_PHY_PAD_FDBK_TERM, |
| 214 | _reg_PHY_PAD_DATA_TERM, |
| 215 | _reg_PHY_PAD_DQS_TERM, |
| 216 | _reg_PHY_PAD_ADDR_TERM, |
| 217 | _reg_PHY_PAD_CLK_TERM, |
| 218 | _reg_PHY_PAD_CKE_TERM, |
| 219 | _reg_PHY_PAD_RST_TERM, |
| 220 | _reg_PHY_PAD_CS_TERM |
| 221 | }; |
| 222 | |
| 223 | #define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10 |
| 224 | static const uint32_t |
| 225 | _reg_PHY_CLK_CACS_SLAVE_DELAY_X[_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = { |
| 226 | _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY, |
| 227 | _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY, |
| 228 | _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY, |
| 229 | _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY, |
| 230 | _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY, |
| 231 | _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY, |
| 232 | |
| 233 | _reg_PHY_GRP_SLAVE_DELAY_0, |
| 234 | _reg_PHY_GRP_SLAVE_DELAY_1, |
| 235 | _reg_PHY_GRP_SLAVE_DELAY_2, |
| 236 | _reg_PHY_GRP_SLAVE_DELAY_3 |
| 237 | }; |
| 238 | |
| 239 | /******************************************************************************* |
| 240 | * Prototypes |
| 241 | ******************************************************************************/ |
| 242 | static inline int32_t vch_nxt(int32_t pos); |
| 243 | static void cpg_write_32(uint32_t a, uint32_t v); |
| 244 | static void pll3_control(uint32_t high); |
| 245 | static inline void dsb_sev(void); |
| 246 | static void wait_dbcmd(void); |
| 247 | static void send_dbcmd(uint32_t cmd); |
| 248 | static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd); |
| 249 | static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata); |
| 250 | static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata); |
| 251 | static inline uint32_t ddr_regdef(uint32_t _regdef); |
| 252 | static inline uint32_t ddr_regdef_adr(uint32_t _regdef); |
| 253 | static inline uint32_t ddr_regdef_lsb(uint32_t _regdef); |
| 254 | static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, |
| 255 | uint32_t val); |
| 256 | static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef); |
| 257 | static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val); |
| 258 | static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val); |
| 259 | static void ddr_setval_ach(uint32_t regdef, uint32_t val); |
| 260 | static void ddr_setval_ach_as(uint32_t regdef, uint32_t val); |
| 261 | static uint32_t ddr_getval(uint32_t ch, uint32_t regdef); |
| 262 | static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t * p); |
| 263 | /* NOT USED |
| 264 | static uint32_t ddr_getval_ach_s(uint32_t slice, uint32_t regdef, uint32_t *p); |
| 265 | */ |
| 266 | static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t * p); |
| 267 | static void _tblcopy(uint32_t * to, const uint32_t * from, uint32_t size); |
| 268 | static void ddrtbl_setval(uint32_t * tbl, uint32_t _regdef, uint32_t val); |
| 269 | static uint32_t ddrtbl_getval(uint32_t * tbl, uint32_t _regdef); |
| 270 | static uint32_t ddrphy_regif_chk(void); |
| 271 | static inline void ddrphy_regif_idle(); |
| 272 | static uint16_t _f_scale(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint32_t ps, |
| 273 | uint16_t cyc); |
| 274 | static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, |
| 275 | uint16_t * js2); |
| 276 | static int16_t _f_scale_adj(int16_t ps); |
| 277 | static void ddrtbl_load(void); |
| 278 | static void ddr_config_sub(void); |
| 279 | static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t * p_swz); |
| 280 | static void ddr_config_sub_h3v1x(void); |
| 281 | static void ddr_config(void); |
| 282 | static void dbsc_regset(void); |
| 283 | static void dbsc_regset_post(void); |
| 284 | static uint32_t dfi_init_start(void); |
| 285 | static void change_lpddr4_en(uint32_t mode); |
| 286 | static uint32_t set_term_code(void); |
| 287 | static void ddr_register_set(uint32_t ch); |
| 288 | static inline uint32_t wait_freqchgreq(uint32_t assert); |
| 289 | static inline void set_freqchgack(uint32_t assert); |
| 290 | static inline void set_dfifrequency(uint32_t freq); |
| 291 | static uint32_t pll3_freq(uint32_t on); |
| 292 | static void update_dly(void); |
| 293 | static uint32_t pi_training_go(void); |
| 294 | static uint32_t init_ddr(void); |
| 295 | static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick); |
| 296 | static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn); |
| 297 | static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn); |
| 298 | static uint32_t wdqdm_man1(void); |
| 299 | static uint32_t wdqdm_man(void); |
| 300 | static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn); |
| 301 | static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn); |
| 302 | static uint32_t rdqdm_man1(void); |
| 303 | static uint32_t rdqdm_man(void); |
| 304 | |
| 305 | static int32_t _find_change(uint64_t val, uint32_t dir); |
| 306 | static uint32_t _rx_offset_cal_updn(uint32_t code); |
| 307 | static uint32_t rx_offset_cal(void); |
| 308 | static uint32_t rx_offset_cal_hw(void); |
| 309 | static void adjust_rddqs_latency(void); |
| 310 | static void adjust_wpath_latency(void); |
| 311 | |
| 312 | struct DdrtData { |
| 313 | int32_t init_temp; /* Initial Temperature (do) */ |
| 314 | uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */ |
| 315 | uint32_t tcomp_cal[4]; /* Temperature compensated io-code (4 is for H3) */ |
| 316 | }; |
| 317 | struct DdrtData tcal; |
| 318 | |
| 319 | static void pvtcode_update(void); |
| 320 | static void pvtcode_update2(void); |
| 321 | static void ddr_padcal_tcompensate_getinit(uint32_t override); |
| 322 | |
| 323 | /******************************************************************************* |
| 324 | * load board configuration |
| 325 | ******************************************************************************/ |
| 326 | #include "boot_init_dram_config.c" |
| 327 | |
| 328 | /******************************************************************************* |
| 329 | * macro for channel selection loop |
| 330 | ******************************************************************************/ |
| 331 | static inline int32_t vch_nxt(int32_t pos) |
| 332 | { |
| 333 | int32_t posn; |
| 334 | |
| 335 | for (posn = pos; posn < DRAM_CH_CNT; posn++) { |
| 336 | if (ddr_phyvalid & (1U << posn)) |
| 337 | break; |
| 338 | } |
| 339 | return posn; |
| 340 | } |
| 341 | |
| 342 | #define foreach_vch(ch) \ |
| 343 | for(ch=vch_nxt(0);ch<DRAM_CH_CNT;ch=vch_nxt(ch+1)) |
| 344 | |
| 345 | #define foreach_ech(ch) \ |
| 346 | for(ch=0;ch<DRAM_CH_CNT;ch++) |
| 347 | |
| 348 | /******************************************************************************* |
| 349 | * Printing functions |
| 350 | ******************************************************************************/ |
| 351 | #define MSG_LF(...) |
| 352 | |
| 353 | /******************************************************************************* |
| 354 | * clock settings, reset control |
| 355 | ******************************************************************************/ |
| 356 | static void cpg_write_32(uint32_t a, uint32_t v) |
| 357 | { |
| 358 | mmio_write_32(CPG_CPGWPR, ~v); |
| 359 | mmio_write_32(a, v); |
| 360 | } |
| 361 | |
| 362 | static void pll3_control(uint32_t high) |
| 363 | { |
| 364 | uint32_t dataL, dataDIV, dataMUL, tmpDIV; |
| 365 | |
| 366 | /* PLL3 disable */ |
| 367 | dataL = mmio_read_32(CPG_PLLECR); |
| 368 | dataL &= ~CPG_PLLECR_PLL3E_BIT; |
| 369 | cpg_write_32(CPG_PLLECR, dataL); |
| 370 | dsb_sev(); |
| 371 | cpg_write_32(CPG_FRQCRD, 0x00030003); /* PLL3 DIV resetting */ |
| 372 | dsb_sev(); |
| 373 | |
| 374 | /* PLL3 enable */ |
| 375 | dataL = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR); |
| 376 | cpg_write_32(CPG_ZB3CKCR, dataL); /* zb3 clk stop */ |
| 377 | dsb_sev(); |
| 378 | |
| 379 | /* PLL3 Restart */ |
| 380 | dataL = mmio_read_32(CPG_PLLECR); |
| 381 | dataL |= CPG_PLLECR_PLL3E_BIT; |
| 382 | cpg_write_32(CPG_PLLECR, dataL); |
| 383 | dsb_sev(); |
| 384 | |
| 385 | do { |
| 386 | dataL = mmio_read_32(CPG_PLLECR); |
| 387 | } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0); |
| 388 | dsb_sev(); |
| 389 | |
| 390 | if (high) { |
| 391 | /* High frequency */ |
| 392 | tmpDIV = |
| 393 | (1000 * ddr_mbpsdiv * brd_clkdiv * (brd_clkdiva + 1)) / |
| 394 | (ddr_mul * brd_clk * ddr_mbpsdiv + 1); |
| 395 | dataMUL = |
| 396 | ((ddr_mul * (tmpDIV + 1) - 1) << 24) | (brd_clkdiva << 7); |
| 397 | if (tmpDIV) { |
| 398 | dataDIV = tmpDIV + 1; |
| 399 | } else { |
| 400 | dataDIV = 0; |
| 401 | } |
| 402 | Pll3Mode = 1; |
| 403 | loop_max = 2; |
| 404 | } else { |
| 405 | /* Low frequency */ |
| 406 | tmpDIV = |
| 407 | (1000 * ddr_mbpsdiv * brd_clkdiv * (brd_clkdiva + 1)) / |
| 408 | (ddr0800_mul * brd_clk * ddr_mbpsdiv + 1); |
| 409 | dataMUL = |
| 410 | ((ddr0800_mul * (tmpDIV + 1) - |
| 411 | 1) << 24) | (brd_clkdiva << 7); |
| 412 | if (tmpDIV) { |
| 413 | dataDIV = tmpDIV + 1; |
| 414 | } else { |
| 415 | dataDIV = 0; |
| 416 | } |
| 417 | Pll3Mode = 0; |
| 418 | loop_max = 8; |
| 419 | } |
| 420 | |
| 421 | dataL = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); |
| 422 | cpg_write_32(CPG_FRQCRD, dataL); /* PLL3 DIV resetting */ |
| 423 | dsb_sev(); |
| 424 | |
| 425 | dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); |
| 426 | cpg_write_32(CPG_FRQCRB, dataL); /* DIV SET KICK */ |
| 427 | dsb_sev(); |
| 428 | |
| 429 | /* PLL3 FREQ */ |
| 430 | cpg_write_32(CPG_PLL3CR, dataMUL); /* Set PLL3 freq */ |
| 431 | dsb_sev(); |
| 432 | |
| 433 | do { |
| 434 | dataL = mmio_read_32(CPG_PLLECR); |
| 435 | } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0); |
| 436 | dsb_sev(); |
| 437 | |
| 438 | dataL = |
| 439 | (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); |
| 440 | cpg_write_32(CPG_FRQCRD, dataL); /* PLL3 DIV resetting */ |
| 441 | dsb_sev(); |
| 442 | |
| 443 | dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); |
| 444 | cpg_write_32(CPG_FRQCRB, dataL); /* DIV SET KICK */ |
| 445 | dsb_sev(); |
| 446 | |
| 447 | do { |
| 448 | dataL = mmio_read_32(CPG_PLLECR); |
| 449 | } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0); |
| 450 | dsb_sev(); |
| 451 | |
| 452 | dataL = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR); |
| 453 | cpg_write_32(CPG_ZB3CKCR, dataL); /* zb3 clk start */ |
| 454 | dsb_sev(); |
| 455 | |
| 456 | return; |
| 457 | } |
| 458 | |
| 459 | /******************************************************************************* |
| 460 | * barrier |
| 461 | ******************************************************************************/ |
| 462 | static inline void dsb_sev(void) |
| 463 | { |
| 464 | __asm__ __volatile__("dsb sy"); |
| 465 | } |
| 466 | |
| 467 | /******************************************************************************* |
| 468 | * DDR memory register access |
| 469 | ******************************************************************************/ |
| 470 | static void wait_dbcmd(void) |
| 471 | { |
| 472 | uint32_t dataL; |
| 473 | /* dummy read */ |
| 474 | dataL = mmio_read_32(DBSC_DBCMD); |
| 475 | dsb_sev(); |
| 476 | while (1) { |
| 477 | /* wait DBCMD 1=busy, 0=ready */ |
| 478 | dataL = mmio_read_32(DBSC_DBWAIT); |
| 479 | dsb_sev(); |
| 480 | if ((dataL & 0x00000001) == 0x00) |
| 481 | break; |
| 482 | } |
| 483 | } |
| 484 | |
| 485 | static void send_dbcmd(uint32_t cmd) |
| 486 | { |
| 487 | /* dummy read */ |
| 488 | wait_dbcmd(); |
| 489 | mmio_write_32(DBSC_DBCMD, cmd); |
| 490 | dsb_sev(); |
| 491 | } |
| 492 | |
| 493 | /******************************************************************************* |
| 494 | * DDRPHY register access (raw) |
| 495 | ******************************************************************************/ |
| 496 | static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd) |
| 497 | { |
| 498 | uint32_t val; |
| 499 | uint32_t loop; |
| 500 | |
| 501 | val = 0; |
| 502 | if ((PRR_PRODUCT_M3N != Prr_Product) |
| 503 | && (PRR_PRODUCT_V3H != Prr_Product)) { |
| 504 | mmio_write_32(DBSC_DBPDRGA(phyno), regadd); |
| 505 | dsb_sev(); |
| 506 | |
| 507 | while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { |
| 508 | dsb_sev(); |
| 509 | } |
| 510 | dsb_sev(); |
| 511 | |
| 512 | for (loop = 0; loop < loop_max; loop++) { |
| 513 | val = mmio_read_32(DBSC_DBPDRGD(phyno)); |
| 514 | dsb_sev(); |
| 515 | } |
| 516 | (void)val; |
| 517 | } else { |
| 518 | mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00004000); |
| 519 | dsb_sev(); |
| 520 | while (mmio_read_32(DBSC_DBPDRGA(phyno)) != |
| 521 | (regadd | 0x0000C000)) { |
| 522 | dsb_sev(); |
| 523 | }; |
| 524 | val = mmio_read_32(DBSC_DBPDRGA(phyno)); |
| 525 | mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); |
| 526 | while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { |
| 527 | dsb_sev(); |
| 528 | }; |
| 529 | dsb_sev(); |
| 530 | |
| 531 | mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); |
| 532 | while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { |
| 533 | dsb_sev(); |
| 534 | }; |
| 535 | |
| 536 | dsb_sev(); |
| 537 | val = mmio_read_32(DBSC_DBPDRGD(phyno)); |
| 538 | dsb_sev(); |
| 539 | (void)val; |
| 540 | } |
| 541 | return val; |
| 542 | } |
| 543 | |
| 544 | static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata) |
| 545 | { |
| 546 | uint32_t val; |
| 547 | uint32_t loop; |
| 548 | |
| 549 | if ((PRR_PRODUCT_M3N != Prr_Product) |
| 550 | && (PRR_PRODUCT_V3H != Prr_Product)) { |
| 551 | mmio_write_32(DBSC_DBPDRGA(phyno), regadd); |
| 552 | dsb_sev(); |
| 553 | for (loop = 0; loop < loop_max; loop++) { |
| 554 | val = mmio_read_32(DBSC_DBPDRGA(phyno)); |
| 555 | dsb_sev(); |
| 556 | } |
| 557 | mmio_write_32(DBSC_DBPDRGD(phyno), regdata); |
| 558 | dsb_sev(); |
| 559 | |
| 560 | for (loop = 0; loop < loop_max; loop++) { |
| 561 | val = mmio_read_32(DBSC_DBPDRGD(phyno)); |
| 562 | dsb_sev(); |
| 563 | } |
| 564 | } else { |
| 565 | mmio_write_32(DBSC_DBPDRGA(phyno), regadd); |
| 566 | dsb_sev(); |
| 567 | |
| 568 | while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { |
| 569 | dsb_sev(); |
| 570 | }; |
| 571 | dsb_sev(); |
| 572 | |
| 573 | mmio_write_32(DBSC_DBPDRGD(phyno), regdata); |
| 574 | dsb_sev(); |
| 575 | |
| 576 | while (mmio_read_32(DBSC_DBPDRGA(phyno)) != |
| 577 | (regadd | 0x00008000)) { |
| 578 | dsb_sev(); |
| 579 | }; |
| 580 | mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); |
| 581 | |
| 582 | while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { |
| 583 | dsb_sev(); |
| 584 | }; |
| 585 | dsb_sev(); |
| 586 | |
| 587 | mmio_write_32(DBSC_DBPDRGA(phyno), regadd); |
| 588 | } |
| 589 | (void)val; |
| 590 | } |
| 591 | |
| 592 | static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata) |
| 593 | { |
| 594 | uint32_t ch; |
| 595 | uint32_t val; |
| 596 | uint32_t loop; |
| 597 | |
| 598 | if ((PRR_PRODUCT_M3N != Prr_Product) |
| 599 | && (PRR_PRODUCT_V3H != Prr_Product)) { |
| 600 | foreach_vch(ch) { |
| 601 | mmio_write_32(DBSC_DBPDRGA(ch), regadd); |
| 602 | dsb_sev(); |
| 603 | } |
| 604 | |
| 605 | foreach_vch(ch) { |
| 606 | mmio_write_32(DBSC_DBPDRGD(ch), regdata); |
| 607 | dsb_sev(); |
| 608 | } |
| 609 | |
| 610 | for (loop = 0; loop < loop_max; loop++) { |
| 611 | val = mmio_read_32(DBSC_DBPDRGD(0)); |
| 612 | dsb_sev(); |
| 613 | } |
| 614 | (void)val; |
| 615 | } else { |
| 616 | foreach_vch(ch) { |
| 617 | reg_ddrphy_write(ch, regadd, regdata); |
| 618 | dsb_sev(); |
| 619 | } |
| 620 | } |
| 621 | } |
| 622 | |
| 623 | static inline void ddrphy_regif_idle() |
| 624 | { |
| 625 | uint32_t val; |
| 626 | |
| 627 | val = reg_ddrphy_read(0, ddr_regdef_adr(_reg_PI_INT_STATUS)); |
| 628 | dsb_sev(); |
| 629 | (void)val; |
| 630 | } |
| 631 | |
| 632 | /******************************************************************************* |
| 633 | * DDRPHY register access (field modify) |
| 634 | ******************************************************************************/ |
| 635 | static inline uint32_t ddr_regdef(uint32_t _regdef) |
| 636 | { |
| 637 | return pDDR_REGDEF_TBL[_regdef]; |
| 638 | } |
| 639 | |
| 640 | static inline uint32_t ddr_regdef_adr(uint32_t _regdef) |
| 641 | { |
| 642 | return DDR_REGDEF_ADR(pDDR_REGDEF_TBL[_regdef]); |
| 643 | } |
| 644 | |
| 645 | static inline uint32_t ddr_regdef_lsb(uint32_t _regdef) |
| 646 | { |
| 647 | return DDR_REGDEF_LSB(pDDR_REGDEF_TBL[_regdef]); |
| 648 | } |
| 649 | |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 650 | static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, |
| 651 | uint32_t val) |
| 652 | { |
| 653 | uint32_t adr; |
| 654 | uint32_t lsb; |
| 655 | uint32_t len; |
| 656 | uint32_t msk; |
| 657 | uint32_t tmp; |
| 658 | uint32_t regdef; |
| 659 | |
| 660 | regdef = ddr_regdef(_regdef); |
| 661 | adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice; |
| 662 | len = DDR_REGDEF_LEN(regdef); |
| 663 | lsb = DDR_REGDEF_LSB(regdef); |
| 664 | if (len == 0x20) |
| 665 | msk = 0xffffffff; |
| 666 | else |
| 667 | msk = ((1U << len) - 1) << lsb; |
| 668 | |
| 669 | tmp = reg_ddrphy_read(ch, adr); |
| 670 | tmp = (tmp & (~msk)) | ((val << lsb) & msk); |
| 671 | reg_ddrphy_write(ch, adr, tmp); |
| 672 | } |
| 673 | |
| 674 | static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef) |
| 675 | { |
| 676 | uint32_t adr; |
| 677 | uint32_t lsb; |
| 678 | uint32_t len; |
| 679 | uint32_t msk; |
| 680 | uint32_t tmp; |
| 681 | uint32_t regdef; |
| 682 | |
| 683 | regdef = ddr_regdef(_regdef); |
| 684 | adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice; |
| 685 | len = DDR_REGDEF_LEN(regdef); |
| 686 | lsb = DDR_REGDEF_LSB(regdef); |
| 687 | if (len == 0x20) |
| 688 | msk = 0xffffffff; |
| 689 | else |
| 690 | msk = ((1U << len) - 1); |
| 691 | |
| 692 | tmp = reg_ddrphy_read(ch, adr); |
| 693 | tmp = (tmp >> lsb) & msk; |
| 694 | |
| 695 | return tmp; |
| 696 | } |
| 697 | |
| 698 | static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val) |
| 699 | { |
| 700 | ddr_setval_s(ch, 0, regdef, val); |
| 701 | } |
| 702 | |
| 703 | static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val) |
| 704 | { |
| 705 | uint32_t ch; |
| 706 | |
| 707 | foreach_vch(ch) |
| 708 | ddr_setval_s(ch, slice, regdef, val); |
| 709 | } |
| 710 | |
| 711 | static void ddr_setval_ach(uint32_t regdef, uint32_t val) |
| 712 | { |
| 713 | ddr_setval_ach_s(0, regdef, val); |
| 714 | } |
| 715 | |
| 716 | static void ddr_setval_ach_as(uint32_t regdef, uint32_t val) |
| 717 | { |
| 718 | uint32_t slice; |
| 719 | |
| 720 | for (slice = 0; slice < SLICE_CNT; slice++) |
| 721 | ddr_setval_ach_s(slice, regdef, val); |
| 722 | } |
| 723 | |
| 724 | static uint32_t ddr_getval(uint32_t ch, uint32_t regdef) |
| 725 | { |
| 726 | return ddr_getval_s(ch, 0, regdef); |
| 727 | } |
| 728 | |
| 729 | static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t * p) |
| 730 | { |
| 731 | uint32_t ch; |
| 732 | |
| 733 | foreach_vch(ch) |
| 734 | p[ch] = ddr_getval_s(ch, 0, regdef); |
| 735 | return p[0]; |
| 736 | } |
| 737 | |
| 738 | /* NOT_USED |
| 739 | static uint32_t ddr_getval_ach_s(uint32_t slice, uint32_t regdef, uint32_t *p) |
| 740 | { |
| 741 | uint32_t ch; |
| 742 | |
| 743 | foreach_vch(ch) |
| 744 | p[ch] = ddr_getval_s(ch, slice, regdef); |
| 745 | return p[0]; |
| 746 | } |
| 747 | */ |
| 748 | |
| 749 | static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t * p) |
| 750 | { |
| 751 | uint32_t ch, slice; |
| 752 | uint32_t *pp; |
| 753 | |
| 754 | pp = p; |
| 755 | foreach_vch(ch) |
| 756 | for (slice = 0; slice < SLICE_CNT; slice++) |
| 757 | *pp++ = ddr_getval_s(ch, slice, regdef); |
| 758 | return p[0]; |
| 759 | } |
| 760 | |
| 761 | /******************************************************************************* |
| 762 | * handling functions for setteing ddrphy value table |
| 763 | ******************************************************************************/ |
| 764 | static void _tblcopy(uint32_t * to, const uint32_t * from, uint32_t size) |
| 765 | { |
| 766 | uint32_t i; |
| 767 | |
| 768 | for (i = 0; i < size; i++) { |
| 769 | to[i] = from[i]; |
| 770 | } |
| 771 | } |
| 772 | |
| 773 | static void ddrtbl_setval(uint32_t * tbl, uint32_t _regdef, uint32_t val) |
| 774 | { |
| 775 | uint32_t adr; |
| 776 | uint32_t lsb; |
| 777 | uint32_t len; |
| 778 | uint32_t msk; |
| 779 | uint32_t tmp; |
| 780 | uint32_t adrmsk; |
| 781 | uint32_t regdef; |
| 782 | |
| 783 | regdef = ddr_regdef(_regdef); |
| 784 | adr = DDR_REGDEF_ADR(regdef); |
| 785 | len = DDR_REGDEF_LEN(regdef); |
| 786 | lsb = DDR_REGDEF_LSB(regdef); |
| 787 | if (len == 0x20) |
| 788 | msk = 0xffffffff; |
| 789 | else |
| 790 | msk = ((1U << len) - 1) << lsb; |
| 791 | |
| 792 | if (adr < 0x400) { |
| 793 | adrmsk = 0xff; |
| 794 | } else { |
| 795 | adrmsk = 0x7f; |
| 796 | } |
| 797 | |
| 798 | tmp = tbl[adr & adrmsk]; |
| 799 | tmp = (tmp & (~msk)) | ((val << lsb) & msk); |
| 800 | tbl[adr & adrmsk] = tmp; |
| 801 | } |
| 802 | |
| 803 | static uint32_t ddrtbl_getval(uint32_t * tbl, uint32_t _regdef) |
| 804 | { |
| 805 | uint32_t adr; |
| 806 | uint32_t lsb; |
| 807 | uint32_t len; |
| 808 | uint32_t msk; |
| 809 | uint32_t tmp; |
| 810 | uint32_t adrmsk; |
| 811 | uint32_t regdef; |
| 812 | |
| 813 | regdef = ddr_regdef(_regdef); |
| 814 | adr = DDR_REGDEF_ADR(regdef); |
| 815 | len = DDR_REGDEF_LEN(regdef); |
| 816 | lsb = DDR_REGDEF_LSB(regdef); |
| 817 | if (len == 0x20) |
| 818 | msk = 0xffffffff; |
| 819 | else |
| 820 | msk = ((1U << len) - 1); |
| 821 | |
| 822 | if (adr < 0x400) { |
| 823 | adrmsk = 0xff; |
| 824 | } else { |
| 825 | adrmsk = 0x7f; |
| 826 | } |
| 827 | |
| 828 | tmp = tbl[adr & adrmsk]; |
| 829 | tmp = (tmp >> lsb) & msk; |
| 830 | |
| 831 | return tmp; |
| 832 | } |
| 833 | |
| 834 | /******************************************************************************* |
| 835 | * DDRPHY register access handling |
| 836 | ******************************************************************************/ |
| 837 | static uint32_t ddrphy_regif_chk(void) |
| 838 | { |
| 839 | uint32_t tmp_ach[DRAM_CH_CNT]; |
| 840 | uint32_t ch; |
| 841 | uint32_t err; |
| 842 | uint32_t PI_VERSION_CODE; |
| 843 | |
| 844 | if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) |
| 845 | || (Prr_Product == PRR_PRODUCT_M3)) { |
| 846 | PI_VERSION_CODE = 0x2041; /* H3 Ver.1.x/M3-W */ |
| 847 | } else { |
| 848 | PI_VERSION_CODE = 0x2040; /* H3 Ver.2.0 or later/M3-N/V3H */ |
| 849 | } |
| 850 | |
| 851 | ddr_getval_ach(_reg_PI_VERSION, (uint32_t *) tmp_ach); |
| 852 | err = 0; |
| 853 | foreach_vch(ch) { |
| 854 | if (PI_VERSION_CODE != tmp_ach[ch]) |
| 855 | err = 1; |
| 856 | } |
| 857 | return err; |
| 858 | } |
| 859 | |
| 860 | /******************************************************************************* |
| 861 | * functions and parameters for timing setting |
| 862 | ******************************************************************************/ |
| 863 | struct _jedec_spec1 { |
| 864 | uint16_t fx3; |
| 865 | uint8_t RLwoDBI; |
| 866 | uint8_t RLwDBI; |
| 867 | uint8_t WL; |
| 868 | uint8_t nWR; |
| 869 | uint8_t nRTP; |
| 870 | uint8_t MR1; |
| 871 | uint8_t MR2; |
| 872 | }; |
| 873 | #define JS1_USABLEC_SPEC_LO 2 |
| 874 | #define JS1_USABLEC_SPEC_HI 5 |
| 875 | #define JS1_FREQ_TBL_NUM 8 |
| 876 | #define JS1_MR1(f) (0x04 | ((f)<<4)) |
| 877 | #define JS1_MR2(f) (0x00 | ((f)<<3) | (f)) |
| 878 | const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = { |
| 879 | /*A { 800, 6, 6, 4, 6 , 8, JS1_MR1(0), JS1_MR2(0) }, 533.333Mbps*/ |
| 880 | /*A { 1600, 10, 12, 6, 10 , 8, JS1_MR1(1), JS1_MR2(1) }, 1066.666Mbps*/ |
| 881 | /*A { 2400, 14, 16, 8, 16 , 8, JS1_MR1(2), JS1_MR2(2) }, 1600.000Mbps*/ |
| 882 | /*B*/ {800, 6, 6, 4, 6, 8, JS1_MR1(0), JS1_MR2(0) | 0x40}, /* 533.333Mbps */ |
| 883 | /*B*/ {1600, 10, 12, 8, 10, 8, JS1_MR1(1), JS1_MR2(1) | 0x40}, /* 1066.666Mbps */ |
| 884 | /*B*/ {2400, 14, 16, 12, 16, 8, JS1_MR1(2), JS1_MR2(2) | 0x40}, /* 1600.000Mbps */ |
| 885 | /*A*/ {3200, 20, 22, 10, 20, 8, JS1_MR1(3), JS1_MR2(3)}, /* 2133.333Mbps */ |
| 886 | /*A*/ {4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4)}, /* 2666.666Mbps */ |
| 887 | /*A*/ {4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5)}, /* 3200.000Mbps */ |
| 888 | /*A*/ {5600, 32, 36, 16, 34, 14, JS1_MR1(6), JS1_MR2(6)}, /* 3733.333Mbps */ |
| 889 | /*A*/ {6400, 36, 40, 18, 40, 16, JS1_MR1(7), JS1_MR2(7)} /* 4266.666Mbps */ |
| 890 | }; |
| 891 | |
| 892 | struct _jedec_spec2 { |
| 893 | uint16_t ps; |
| 894 | uint16_t cyc; |
| 895 | }; |
| 896 | |
| 897 | #define JS2_tSR 0 |
| 898 | #define JS2_tXP 1 |
| 899 | #define JS2_tRTP 2 |
| 900 | #define JS2_tRCD 3 |
| 901 | #define JS2_tRPpb 4 |
| 902 | #define JS2_tRPab 5 |
| 903 | #define JS2_tRAS 6 |
| 904 | #define JS2_tWR 7 |
| 905 | #define JS2_tWTR 8 |
| 906 | #define JS2_tRRD 9 |
| 907 | #define JS2_tPPD 10 |
| 908 | #define JS2_tFAW 11 |
| 909 | #define JS2_tDQSCK 12 |
| 910 | #define JS2_tCKEHCMD 13 |
| 911 | #define JS2_tCKELCMD 14 |
| 912 | #define JS2_tCKELPD 15 |
| 913 | #define JS2_tMRR 16 |
| 914 | #define JS2_tMRW 17 |
| 915 | #define JS2_tMRD 18 |
| 916 | #define JS2_tZQCALns 19 |
| 917 | #define JS2_tZQLAT 20 |
| 918 | #define JS2_tIEdly 21 |
| 919 | #define JS2_TBLCNT 22 |
| 920 | |
| 921 | #define JS2_tRCpb (JS2_TBLCNT) |
| 922 | #define JS2_tRCab (JS2_TBLCNT+1) |
| 923 | #define JS2_tRFCpb (JS2_TBLCNT+2) |
| 924 | #define JS2_tRFCab (JS2_TBLCNT+3) |
| 925 | #define JS2_CNT (JS2_TBLCNT+4) |
| 926 | |
| 927 | #ifndef JS2_DERATE |
| 928 | #define JS2_DERATE 0 |
| 929 | #endif |
| 930 | const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = { |
| 931 | { |
| 932 | /*tSR */ {15000, 3}, |
| 933 | /*tXP */ {7500, 3}, |
| 934 | /*tRTP */ {7500, 8}, |
| 935 | /*tRCD */ {18000, 4}, |
| 936 | /*tRPpb */ {18000, 3}, |
| 937 | /*tRPab */ {21000, 3}, |
| 938 | /*tRAS */ {42000, 3}, |
| 939 | /*tWR */ {18000, 4}, |
| 940 | /*tWTR */ {10000, 8}, |
| 941 | /*tRRD */ {10000, 4}, |
| 942 | /*tPPD */ {0, 0}, |
| 943 | /*tFAW */ {40000, 0}, |
| 944 | /*tDQSCK*/ {3500, 0}, |
| 945 | /*tCKEHCMD*/ {7500, 3}, |
| 946 | /*tCKELCMD*/ {7500, 3}, |
| 947 | /*tCKELPD*/ {7500, 3}, |
| 948 | /*tMRR*/ {0, 8}, |
| 949 | /*tMRW*/ {10000, 10}, |
| 950 | /*tMRD*/ {14000, 10}, |
| 951 | /*tZQCALns*/ {1000 * 10, 0}, |
| 952 | /*tZQLAT*/ {30000, 10}, |
| 953 | /*tIEdly*/ {12500, 0} |
| 954 | }, { |
| 955 | /*tSR */ {15000, 3}, |
| 956 | /*tXP */ {7500, 3}, |
| 957 | /*tRTP */ {7500, 8}, |
| 958 | /*tRCD */ {19875, 4}, |
| 959 | /*tRPpb */ {19875, 3}, |
| 960 | /*tRPab */ {22875, 3}, |
| 961 | /*tRAS */ {43875, 3}, |
| 962 | /*tWR */ {18000, 4}, |
| 963 | /*tWTR */ {10000, 8}, |
| 964 | /*tRRD */ {11875, 4}, |
| 965 | /*tPPD */ {0, 0}, |
| 966 | /*tFAW */ {40000, 0}, |
| 967 | /*tDQSCK*/ {3600, 0}, |
| 968 | /*tCKEHCMD*/ {7500, 3}, |
| 969 | /*tCKELCMD*/ {7500, 3}, |
| 970 | /*tCKELPD*/ {7500, 3}, |
| 971 | /*tMRR*/ {0, 8}, |
| 972 | /*tMRW*/ {10000, 10}, |
| 973 | /*tMRD*/ {14000, 10}, |
| 974 | /*tZQCALns*/ {1000 * 10, 0}, |
| 975 | /*tZQLAT*/ {30000, 10}, |
| 976 | /*tIEdly*/ {12500, 0} |
| 977 | } |
| 978 | }; |
| 979 | |
| 980 | /* pb, ab */ |
| 981 | const uint16_t jedec_spec2_tRFC_pb_ab[2][7] = { |
| 982 | /* 4Gb, 6Gb, 8Gb,12Gb, 16Gb, 24Gb(non), 32Gb(non) */ |
| 983 | { |
| 984 | 60, 90, 90, 140, 140, 280, 280}, |
| 985 | { |
| 986 | 130, 180, 180, 280, 280, 560, 560} |
| 987 | }; |
| 988 | |
| 989 | static uint32_t js1_ind; |
| 990 | static uint16_t js2[JS2_CNT]; |
| 991 | static uint8_t RL; |
| 992 | static uint8_t WL; |
| 993 | |
| 994 | static uint16_t _f_scale(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint32_t ps, |
| 995 | uint16_t cyc) |
| 996 | { |
| 997 | uint32_t tmp; |
| 998 | uint32_t div; |
| 999 | |
| 1000 | tmp = (((uint32_t) (ps) + 9) / 10) * ddr_mbps; |
| 1001 | div = tmp / (200000 * ddr_mbpsdiv); |
| 1002 | if (tmp != (div * 200000 * ddr_mbpsdiv)) |
| 1003 | div = div + 1; |
| 1004 | |
| 1005 | if (div > cyc) |
| 1006 | return (uint16_t) div; |
| 1007 | return cyc; |
| 1008 | } |
| 1009 | |
| 1010 | static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, |
| 1011 | uint16_t * js2) |
| 1012 | { |
| 1013 | int i; |
| 1014 | |
| 1015 | for (i = 0; i < JS2_TBLCNT; i++) { |
| 1016 | js2[i] = _f_scale(ddr_mbps, ddr_mbpsdiv, |
| 1017 | 1UL * jedec_spec2[JS2_DERATE][i].ps, |
| 1018 | jedec_spec2[JS2_DERATE][i].cyc); |
| 1019 | } |
| 1020 | |
| 1021 | js2[JS2_tRCpb] = js2[JS2_tRAS] + js2[JS2_tRPpb]; |
| 1022 | js2[JS2_tRCab] = js2[JS2_tRAS] + js2[JS2_tRPab]; |
| 1023 | } |
| 1024 | |
| 1025 | /* scaler for DELAY value */ |
| 1026 | static int16_t _f_scale_adj(int16_t ps) |
| 1027 | { |
| 1028 | int32_t tmp; |
| 1029 | /* |
| 1030 | tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000; |
| 1031 | = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125 |
| 1032 | = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125 |
| 1033 | */ |
| 1034 | tmp = |
| 1035 | (int32_t) 4 *(int32_t) ps *(int32_t) ddr_mbps / |
| 1036 | (int32_t) ddr_mbpsdiv; |
| 1037 | tmp = (int32_t) tmp / (int32_t) 15625; |
| 1038 | |
| 1039 | return (int16_t) tmp; |
| 1040 | } |
| 1041 | |
| 1042 | const uint32_t _reg_PI_MR1_DATA_Fx_CSx[2][CSAB_CNT] = { |
| 1043 | { |
| 1044 | _reg_PI_MR1_DATA_F0_0, |
| 1045 | _reg_PI_MR1_DATA_F0_1, |
| 1046 | _reg_PI_MR1_DATA_F0_2, |
| 1047 | _reg_PI_MR1_DATA_F0_3}, |
| 1048 | { |
| 1049 | _reg_PI_MR1_DATA_F1_0, |
| 1050 | _reg_PI_MR1_DATA_F1_1, |
| 1051 | _reg_PI_MR1_DATA_F1_2, |
| 1052 | _reg_PI_MR1_DATA_F1_3} |
| 1053 | }; |
| 1054 | |
| 1055 | const uint32_t _reg_PI_MR2_DATA_Fx_CSx[2][CSAB_CNT] = { |
| 1056 | { |
| 1057 | _reg_PI_MR2_DATA_F0_0, |
| 1058 | _reg_PI_MR2_DATA_F0_1, |
| 1059 | _reg_PI_MR2_DATA_F0_2, |
| 1060 | _reg_PI_MR2_DATA_F0_3}, |
| 1061 | { |
| 1062 | _reg_PI_MR2_DATA_F1_0, |
| 1063 | _reg_PI_MR2_DATA_F1_1, |
| 1064 | _reg_PI_MR2_DATA_F1_2, |
| 1065 | _reg_PI_MR2_DATA_F1_3} |
| 1066 | }; |
| 1067 | |
| 1068 | const uint32_t _reg_PI_MR3_DATA_Fx_CSx[2][CSAB_CNT] = { |
| 1069 | { |
| 1070 | _reg_PI_MR3_DATA_F0_0, |
| 1071 | _reg_PI_MR3_DATA_F0_1, |
| 1072 | _reg_PI_MR3_DATA_F0_2, |
| 1073 | _reg_PI_MR3_DATA_F0_3}, |
| 1074 | { |
| 1075 | _reg_PI_MR3_DATA_F1_0, |
| 1076 | _reg_PI_MR3_DATA_F1_1, |
| 1077 | _reg_PI_MR3_DATA_F1_2, |
| 1078 | _reg_PI_MR3_DATA_F1_3} |
| 1079 | }; |
| 1080 | |
| 1081 | const uint32_t _reg_PI_MR11_DATA_Fx_CSx[2][CSAB_CNT] = { |
| 1082 | { |
| 1083 | _reg_PI_MR11_DATA_F0_0, |
| 1084 | _reg_PI_MR11_DATA_F0_1, |
| 1085 | _reg_PI_MR11_DATA_F0_2, |
| 1086 | _reg_PI_MR11_DATA_F0_3}, |
| 1087 | { |
| 1088 | _reg_PI_MR11_DATA_F1_0, |
| 1089 | _reg_PI_MR11_DATA_F1_1, |
| 1090 | _reg_PI_MR11_DATA_F1_2, |
| 1091 | _reg_PI_MR11_DATA_F1_3} |
| 1092 | }; |
| 1093 | |
| 1094 | const uint32_t _reg_PI_MR12_DATA_Fx_CSx[2][CSAB_CNT] = { |
| 1095 | { |
| 1096 | _reg_PI_MR12_DATA_F0_0, |
| 1097 | _reg_PI_MR12_DATA_F0_1, |
| 1098 | _reg_PI_MR12_DATA_F0_2, |
| 1099 | _reg_PI_MR12_DATA_F0_3}, |
| 1100 | { |
| 1101 | _reg_PI_MR12_DATA_F1_0, |
| 1102 | _reg_PI_MR12_DATA_F1_1, |
| 1103 | _reg_PI_MR12_DATA_F1_2, |
| 1104 | _reg_PI_MR12_DATA_F1_3} |
| 1105 | }; |
| 1106 | |
| 1107 | const uint32_t _reg_PI_MR14_DATA_Fx_CSx[2][CSAB_CNT] = { |
| 1108 | { |
| 1109 | _reg_PI_MR14_DATA_F0_0, |
| 1110 | _reg_PI_MR14_DATA_F0_1, |
| 1111 | _reg_PI_MR14_DATA_F0_2, |
| 1112 | _reg_PI_MR14_DATA_F0_3}, |
| 1113 | { |
| 1114 | _reg_PI_MR14_DATA_F1_0, |
| 1115 | _reg_PI_MR14_DATA_F1_1, |
| 1116 | _reg_PI_MR14_DATA_F1_2, |
| 1117 | _reg_PI_MR14_DATA_F1_3} |
| 1118 | }; |
| 1119 | |
| 1120 | /******************************************************************************* |
| 1121 | * regif pll w/a ( REGIF H3 Ver.2.0 or later/M3-N/V3H WA ) |
| 1122 | *******************************************************************************/ |
| 1123 | static void regif_pll_wa(void) |
| 1124 | { |
| 1125 | uint32_t ch; |
| 1126 | |
| 1127 | if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { |
| 1128 | reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT), |
| 1129 | (0x0064U << |
| 1130 | ddr_regdef_lsb(_reg_PHY_PLL_WAIT))); |
| 1131 | reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), |
| 1132 | ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, |
| 1133 | _reg_PHY_PLL_CTRL)); |
| 1134 | |
| 1135 | reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL), |
| 1136 | ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, |
| 1137 | _reg_PHY_LP4_BOOT_PLL_CTRL)); |
| 1138 | |
| 1139 | } else { |
| 1140 | /* PLL setting for PHY : M3-W/M3-N/V3H/H3 Ver.2.0 or later */ |
| 1141 | reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT), |
| 1142 | (0x5064U << |
| 1143 | ddr_regdef_lsb(_reg_PHY_PLL_WAIT))); |
| 1144 | |
| 1145 | reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), |
| 1146 | (ddrtbl_getval |
| 1147 | (_cnf_DDR_PHY_ADR_G_REGSET, |
| 1148 | _reg_PHY_PLL_CTRL_TOP) << 16) | |
| 1149 | ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, |
| 1150 | _reg_PHY_PLL_CTRL)); |
| 1151 | reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA), |
| 1152 | ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, |
| 1153 | _reg_PHY_PLL_CTRL_CA)); |
| 1154 | |
| 1155 | reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL), |
| 1156 | (ddrtbl_getval |
| 1157 | (_cnf_DDR_PHY_ADR_G_REGSET, |
| 1158 | _reg_PHY_LP4_BOOT_PLL_CTRL_CA) << 16) | |
| 1159 | ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, |
| 1160 | _reg_PHY_LP4_BOOT_PLL_CTRL)); |
| 1161 | reg_ddrphy_write_a(ddr_regdef_adr |
| 1162 | (_reg_PHY_LP4_BOOT_TOP_PLL_CTRL), |
| 1163 | ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, |
| 1164 | _reg_PHY_LP4_BOOT_TOP_PLL_CTRL)); |
| 1165 | } |
| 1166 | |
| 1167 | /* protect register interface */ |
| 1168 | ddrphy_regif_idle(); |
| 1169 | pll3_control(0); |
| 1170 | |
| 1171 | if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { |
| 1172 | /* non */ |
| 1173 | } else { |
| 1174 | reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_DLL_RST_EN), |
| 1175 | (0x01U << |
| 1176 | ddr_regdef_lsb(_reg_PHY_DLL_RST_EN))); |
| 1177 | ddrphy_regif_idle(); |
| 1178 | } |
| 1179 | |
| 1180 | /*********************************************************************** |
| 1181 | init start |
| 1182 | ***********************************************************************/ |
| 1183 | /* dbdficnt0: |
| 1184 | * dfi_dram_clk_disable=1 |
| 1185 | * dfi_frequency = 0 |
| 1186 | * freq_ratio = 01 (2:1) |
| 1187 | * init_start =0 |
| 1188 | */ |
| 1189 | foreach_vch(ch) |
| 1190 | mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10); |
| 1191 | dsb_sev(); |
| 1192 | |
| 1193 | /* dbdficnt0: |
| 1194 | * dfi_dram_clk_disable=1 |
| 1195 | * dfi_frequency = 0 |
| 1196 | * freq_ratio = 01 (2:1) |
| 1197 | * init_start =1 |
| 1198 | */ |
| 1199 | foreach_vch(ch) |
| 1200 | mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11); |
| 1201 | dsb_sev(); |
| 1202 | |
| 1203 | foreach_ech(ch) |
| 1204 | if (((Boardcnf->phyvalid) & (1U << ch))) |
| 1205 | while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f) ; |
| 1206 | dsb_sev(); |
| 1207 | } |
| 1208 | |
| 1209 | /******************************************************************************* |
| 1210 | * load table data into DDR registers |
| 1211 | ******************************************************************************/ |
| 1212 | static void ddrtbl_load(void) |
| 1213 | { |
| 1214 | int i; |
| 1215 | uint32_t slice; |
| 1216 | uint32_t csab; |
| 1217 | uint32_t adr; |
| 1218 | uint32_t dataL; |
| 1219 | uint32_t tmp[3]; |
| 1220 | uint16_t dataS; |
| 1221 | |
| 1222 | /*********************************************************************** |
| 1223 | TIMING REGISTERS |
| 1224 | ***********************************************************************/ |
| 1225 | /* search jedec_spec1 index */ |
| 1226 | for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) { |
| 1227 | if (js1[i].fx3 * 2 * ddr_mbpsdiv >= ddr_mbps * 3) |
| 1228 | break; |
| 1229 | } |
| 1230 | if (JS1_USABLEC_SPEC_HI < i) |
| 1231 | js1_ind = JS1_USABLEC_SPEC_HI; |
| 1232 | else |
| 1233 | js1_ind = i; |
| 1234 | |
| 1235 | if (Boardcnf->dbi_en) |
| 1236 | RL = js1[js1_ind].RLwDBI; |
| 1237 | else |
| 1238 | RL = js1[js1_ind].RLwoDBI; |
| 1239 | |
| 1240 | WL = js1[js1_ind].WL; |
| 1241 | |
| 1242 | /* calculate jedec_spec2 */ |
| 1243 | _f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2); |
| 1244 | |
| 1245 | /*********************************************************************** |
| 1246 | PREPARE TBL |
| 1247 | ***********************************************************************/ |
| 1248 | if (Prr_Product == PRR_PRODUCT_H3) { |
| 1249 | if (Prr_Cut <= PRR_PRODUCT_11) { |
| 1250 | /* H3 Ver.1.x */ |
| 1251 | _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, |
| 1252 | DDR_PHY_SLICE_REGSET_H3, |
| 1253 | DDR_PHY_SLICE_REGSET_NUM_H3); |
| 1254 | _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, |
| 1255 | DDR_PHY_ADR_V_REGSET_H3, |
| 1256 | DDR_PHY_ADR_V_REGSET_NUM_H3); |
| 1257 | _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, |
| 1258 | DDR_PHY_ADR_I_REGSET_H3, |
| 1259 | DDR_PHY_ADR_I_REGSET_NUM_H3); |
| 1260 | _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, |
| 1261 | DDR_PHY_ADR_G_REGSET_H3, |
| 1262 | DDR_PHY_ADR_G_REGSET_NUM_H3); |
| 1263 | _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_H3, |
| 1264 | DDR_PI_REGSET_NUM_H3); |
| 1265 | |
| 1266 | DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_H3; |
| 1267 | DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_H3; |
| 1268 | DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_H3; |
| 1269 | DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_H3; |
| 1270 | DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_H3; |
| 1271 | DDR_PHY_SLICE_REGSET_SIZE = |
| 1272 | DDR_PHY_SLICE_REGSET_SIZE_H3; |
| 1273 | DDR_PHY_ADR_V_REGSET_SIZE = |
| 1274 | DDR_PHY_ADR_V_REGSET_SIZE_H3; |
| 1275 | DDR_PHY_ADR_I_REGSET_SIZE = |
| 1276 | DDR_PHY_ADR_I_REGSET_SIZE_H3; |
| 1277 | DDR_PHY_ADR_G_REGSET_SIZE = |
| 1278 | DDR_PHY_ADR_G_REGSET_SIZE_H3; |
| 1279 | DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_H3; |
| 1280 | DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_H3; |
| 1281 | DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_H3; |
| 1282 | DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_H3; |
| 1283 | DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_H3; |
| 1284 | DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_H3; |
| 1285 | |
| 1286 | DDR_PHY_ADR_I_NUM = 1; |
| 1287 | } else { |
| 1288 | /* H3 Ver.2.0 or later */ |
| 1289 | _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, |
| 1290 | DDR_PHY_SLICE_REGSET_H3VER2, |
| 1291 | DDR_PHY_SLICE_REGSET_NUM_H3VER2); |
| 1292 | _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, |
| 1293 | DDR_PHY_ADR_V_REGSET_H3VER2, |
| 1294 | DDR_PHY_ADR_V_REGSET_NUM_H3VER2); |
| 1295 | _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, |
| 1296 | DDR_PHY_ADR_G_REGSET_H3VER2, |
| 1297 | DDR_PHY_ADR_G_REGSET_NUM_H3VER2); |
| 1298 | _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_H3VER2, |
| 1299 | DDR_PI_REGSET_NUM_H3VER2); |
| 1300 | |
| 1301 | DDR_PHY_SLICE_REGSET_OFS = |
| 1302 | DDR_PHY_SLICE_REGSET_OFS_H3VER2; |
| 1303 | DDR_PHY_ADR_V_REGSET_OFS = |
| 1304 | DDR_PHY_ADR_V_REGSET_OFS_H3VER2; |
| 1305 | DDR_PHY_ADR_G_REGSET_OFS = |
| 1306 | DDR_PHY_ADR_G_REGSET_OFS_H3VER2; |
| 1307 | DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_H3VER2; |
| 1308 | DDR_PHY_SLICE_REGSET_SIZE = |
| 1309 | DDR_PHY_SLICE_REGSET_SIZE_H3VER2; |
| 1310 | DDR_PHY_ADR_V_REGSET_SIZE = |
| 1311 | DDR_PHY_ADR_V_REGSET_SIZE_H3VER2; |
| 1312 | DDR_PHY_ADR_G_REGSET_SIZE = |
| 1313 | DDR_PHY_ADR_G_REGSET_SIZE_H3VER2; |
| 1314 | DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_H3VER2; |
| 1315 | DDR_PHY_SLICE_REGSET_NUM = |
| 1316 | DDR_PHY_SLICE_REGSET_NUM_H3VER2; |
| 1317 | DDR_PHY_ADR_V_REGSET_NUM = |
| 1318 | DDR_PHY_ADR_V_REGSET_NUM_H3VER2; |
| 1319 | DDR_PHY_ADR_G_REGSET_NUM = |
| 1320 | DDR_PHY_ADR_G_REGSET_NUM_H3VER2; |
| 1321 | DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_H3VER2; |
| 1322 | |
| 1323 | DDR_PHY_ADR_I_NUM = 0; |
| 1324 | } |
| 1325 | } else if (Prr_Product == PRR_PRODUCT_M3) { |
| 1326 | /* M3-W */ |
| 1327 | _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, |
| 1328 | DDR_PHY_SLICE_REGSET_M3, DDR_PHY_SLICE_REGSET_NUM_M3); |
| 1329 | _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, |
| 1330 | DDR_PHY_ADR_V_REGSET_M3, DDR_PHY_ADR_V_REGSET_NUM_M3); |
| 1331 | _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, |
| 1332 | DDR_PHY_ADR_I_REGSET_M3, DDR_PHY_ADR_I_REGSET_NUM_M3); |
| 1333 | _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, |
| 1334 | DDR_PHY_ADR_G_REGSET_M3, DDR_PHY_ADR_G_REGSET_NUM_M3); |
| 1335 | _tblcopy(_cnf_DDR_PI_REGSET, |
| 1336 | DDR_PI_REGSET_M3, DDR_PI_REGSET_NUM_M3); |
| 1337 | |
| 1338 | DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_M3; |
| 1339 | DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_M3; |
| 1340 | DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_M3; |
| 1341 | DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_M3; |
| 1342 | DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_M3; |
| 1343 | DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_M3; |
| 1344 | DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_M3; |
| 1345 | DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_M3; |
| 1346 | DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_M3; |
| 1347 | DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_M3; |
| 1348 | DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_M3; |
| 1349 | DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_M3; |
| 1350 | DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_M3; |
| 1351 | DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_M3; |
| 1352 | DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_M3; |
| 1353 | |
| 1354 | DDR_PHY_ADR_I_NUM = 2; |
| 1355 | } else { |
| 1356 | /* M3-N/V3H */ |
| 1357 | _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, |
| 1358 | DDR_PHY_SLICE_REGSET_M3N, |
| 1359 | DDR_PHY_SLICE_REGSET_NUM_M3N); |
| 1360 | _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, DDR_PHY_ADR_V_REGSET_M3N, |
| 1361 | DDR_PHY_ADR_V_REGSET_NUM_M3N); |
| 1362 | _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, DDR_PHY_ADR_I_REGSET_M3N, |
| 1363 | DDR_PHY_ADR_I_REGSET_NUM_M3N); |
| 1364 | _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, DDR_PHY_ADR_G_REGSET_M3N, |
| 1365 | DDR_PHY_ADR_G_REGSET_NUM_M3N); |
| 1366 | _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_M3N, |
| 1367 | DDR_PI_REGSET_NUM_M3N); |
| 1368 | |
| 1369 | DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_M3N; |
| 1370 | DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_M3N; |
| 1371 | DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_M3N; |
| 1372 | DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_M3N; |
| 1373 | DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_M3N; |
| 1374 | DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_M3N; |
| 1375 | DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_M3N; |
| 1376 | DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_M3N; |
| 1377 | DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_M3N; |
| 1378 | DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_M3N; |
| 1379 | DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_M3N; |
| 1380 | DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_M3N; |
| 1381 | DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_M3N; |
| 1382 | DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_M3N; |
| 1383 | DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_M3N; |
| 1384 | |
| 1385 | DDR_PHY_ADR_I_NUM = 2; |
| 1386 | } |
| 1387 | |
| 1388 | /*********************************************************************** |
| 1389 | PLL CODE CHANGE |
| 1390 | ***********************************************************************/ |
| 1391 | if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_11)) { |
| 1392 | ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL, |
| 1393 | 0x1142); |
| 1394 | ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, |
| 1395 | _reg_PHY_LP4_BOOT_PLL_CTRL, 0x1142); |
| 1396 | } |
| 1397 | |
| 1398 | /*********************************************************************** |
| 1399 | on fly gate adjust |
| 1400 | ***********************************************************************/ |
| 1401 | if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut == PRR_PRODUCT_10)) { |
| 1402 | ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, |
| 1403 | _reg_ON_FLY_GATE_ADJUST_EN, 0x00); |
| 1404 | } |
| 1405 | |
| 1406 | /*********************************************************************** |
| 1407 | Adjust PI paramters |
| 1408 | ***********************************************************************/ |
| 1409 | #ifdef _def_LPDDR4_ODT |
| 1410 | ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F0_0, |
| 1411 | _def_LPDDR4_ODT); |
| 1412 | ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F0_1, |
| 1413 | _def_LPDDR4_ODT); |
| 1414 | ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F0_2, |
| 1415 | _def_LPDDR4_ODT); |
| 1416 | ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F0_3, |
| 1417 | _def_LPDDR4_ODT); |
| 1418 | |
| 1419 | ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F1_0, |
| 1420 | _def_LPDDR4_ODT); |
| 1421 | ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F1_1, |
| 1422 | _def_LPDDR4_ODT); |
| 1423 | ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F1_2, |
| 1424 | _def_LPDDR4_ODT); |
| 1425 | ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F1_3, |
| 1426 | _def_LPDDR4_ODT); |
| 1427 | #endif /* _def_LPDDR4_ODT */ |
| 1428 | |
| 1429 | #ifdef _def_LPDDR4_VREFCA |
| 1430 | ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F0_0, |
| 1431 | _def_LPDDR4_VREFCA); |
| 1432 | ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F0_1, |
| 1433 | _def_LPDDR4_VREFCA); |
| 1434 | ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F0_2, |
| 1435 | _def_LPDDR4_VREFCA); |
| 1436 | ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F0_3, |
| 1437 | _def_LPDDR4_VREFCA); |
| 1438 | |
| 1439 | ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F1_0, |
| 1440 | _def_LPDDR4_VREFCA); |
| 1441 | ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F1_1, |
| 1442 | _def_LPDDR4_VREFCA); |
| 1443 | ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F1_2, |
| 1444 | _def_LPDDR4_VREFCA); |
| 1445 | ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F1_3, |
| 1446 | _def_LPDDR4_VREFCA); |
| 1447 | #endif /* _def_LPDDR4_VREFCA */ |
| 1448 | if ((Prr_Product == PRR_PRODUCT_M3N) |
| 1449 | || (Prr_Product == PRR_PRODUCT_V3H)) { |
| 1450 | js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7; |
| 1451 | if (js2[JS2_tIEdly] > (RL)) |
| 1452 | js2[JS2_tIEdly] = RL; |
| 1453 | } else if ((Prr_Product == PRR_PRODUCT_H3) |
| 1454 | && (Prr_Cut > PRR_PRODUCT_11)) { |
| 1455 | js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4; |
| 1456 | } else if ((Prr_Product == PRR_PRODUCT_H3) |
| 1457 | && (Prr_Cut <= PRR_PRODUCT_11)) { |
| 1458 | js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0); |
| 1459 | } |
| 1460 | |
| 1461 | if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) |
| 1462 | || (Prr_Product == PRR_PRODUCT_M3N) |
| 1463 | || (Prr_Product == PRR_PRODUCT_V3H)) { |
| 1464 | if ((js2[JS2_tIEdly]) >= 0x1e) |
| 1465 | dataS = 0x1e; |
| 1466 | else |
| 1467 | dataS = js2[JS2_tIEdly]; |
| 1468 | } else { |
| 1469 | if ((js2[JS2_tIEdly]) >= 0x0e) |
| 1470 | dataS = 0x0e; |
| 1471 | else |
| 1472 | dataS = js2[JS2_tIEdly]; |
| 1473 | } |
| 1474 | |
| 1475 | ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS); |
| 1476 | ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY, |
| 1477 | (dataS - 2)); |
| 1478 | if ((Prr_Product == PRR_PRODUCT_M3N) |
| 1479 | || (Prr_Product == PRR_PRODUCT_V3H)) { |
| 1480 | ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, |
| 1481 | _reg_PHY_RDDATA_EN_OE_DLY, dataS); |
| 1482 | } |
| 1483 | ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataS); |
| 1484 | |
| 1485 | if (ddrtbl_getval |
| 1486 | (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) { |
| 1487 | dataL = WL - 1; |
| 1488 | } else { |
| 1489 | dataL = WL; |
| 1490 | } |
| 1491 | ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, dataL - 2); |
| 1492 | ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, dataL); |
| 1493 | |
| 1494 | if (Boardcnf->dbi_en) { |
| 1495 | ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE, |
| 1496 | 0x01); |
| 1497 | ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, |
| 1498 | _reg_PHY_WDQLVL_DATADM_MASK, 0x000); |
| 1499 | } else { |
| 1500 | ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE, |
| 1501 | 0x00); |
| 1502 | ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, |
| 1503 | _reg_PHY_WDQLVL_DATADM_MASK, 0x100); |
| 1504 | } |
| 1505 | |
| 1506 | tmp[0] = js1[js1_ind].MR1; |
| 1507 | tmp[1] = js1[js1_ind].MR2; |
| 1508 | dataL = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0); |
| 1509 | if (Boardcnf->dbi_en) |
| 1510 | tmp[2] = dataL | 0xc0; |
| 1511 | else |
| 1512 | tmp[2] = dataL & (~0xc0); |
| 1513 | |
| 1514 | for (i = 0; i < 2; i++) { |
| 1515 | for (csab = 0; csab < CSAB_CNT; csab++) { |
| 1516 | ddrtbl_setval(_cnf_DDR_PI_REGSET, |
| 1517 | _reg_PI_MR1_DATA_Fx_CSx[i][csab], tmp[0]); |
| 1518 | ddrtbl_setval(_cnf_DDR_PI_REGSET, |
| 1519 | _reg_PI_MR2_DATA_Fx_CSx[i][csab], tmp[1]); |
| 1520 | ddrtbl_setval(_cnf_DDR_PI_REGSET, |
| 1521 | _reg_PI_MR3_DATA_Fx_CSx[i][csab], tmp[2]); |
| 1522 | } |
| 1523 | } |
| 1524 | |
| 1525 | /*********************************************************************** |
| 1526 | DDRPHY INT START |
| 1527 | ***********************************************************************/ |
| 1528 | if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { |
| 1529 | /* non */ |
| 1530 | } else { |
| 1531 | regif_pll_wa(); |
| 1532 | } |
| 1533 | |
| 1534 | /*********************************************************************** |
| 1535 | FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) |
| 1536 | ***********************************************************************/ |
| 1537 | ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x01); |
| 1538 | ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01); |
| 1539 | |
| 1540 | /*********************************************************************** |
| 1541 | SET DATA SLICE TABLE |
| 1542 | ***********************************************************************/ |
| 1543 | for (slice = 0; slice < SLICE_CNT; slice++) { |
| 1544 | adr = |
| 1545 | DDR_PHY_SLICE_REGSET_OFS + |
| 1546 | DDR_PHY_SLICE_REGSET_SIZE * slice; |
| 1547 | for (i = 0; i < DDR_PHY_SLICE_REGSET_NUM; i++) { |
| 1548 | reg_ddrphy_write_a(adr + i, |
| 1549 | _cnf_DDR_PHY_SLICE_REGSET[i]); |
| 1550 | } |
| 1551 | } |
| 1552 | |
| 1553 | /*********************************************************************** |
| 1554 | SET ADR SLICE TABLE |
| 1555 | ***********************************************************************/ |
| 1556 | adr = DDR_PHY_ADR_V_REGSET_OFS; |
| 1557 | for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) { |
| 1558 | reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]); |
| 1559 | } |
| 1560 | |
| 1561 | if (DDR_PHY_ADR_I_NUM > 0) { |
| 1562 | for (slice = 0; slice < DDR_PHY_ADR_I_NUM; slice++) { |
| 1563 | adr = |
| 1564 | DDR_PHY_ADR_I_REGSET_OFS + |
| 1565 | DDR_PHY_ADR_I_REGSET_SIZE * slice; |
| 1566 | for (i = 0; i < DDR_PHY_ADR_I_REGSET_NUM; i++) { |
| 1567 | reg_ddrphy_write_a(adr + i, |
| 1568 | _cnf_DDR_PHY_ADR_I_REGSET |
| 1569 | [i]); |
| 1570 | } |
| 1571 | } |
| 1572 | } |
| 1573 | |
| 1574 | /*********************************************************************** |
| 1575 | SET ADRCTRL SLICE TABLE |
| 1576 | ***********************************************************************/ |
| 1577 | adr = DDR_PHY_ADR_G_REGSET_OFS; |
| 1578 | for (i = 0; i < DDR_PHY_ADR_G_REGSET_NUM; i++) { |
| 1579 | reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]); |
| 1580 | } |
| 1581 | |
| 1582 | /*********************************************************************** |
| 1583 | SET PI REGISTERS |
| 1584 | ***********************************************************************/ |
| 1585 | adr = DDR_PI_REGSET_OFS; |
| 1586 | for (i = 0; i < DDR_PI_REGSET_NUM; i++) { |
| 1587 | reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]); |
| 1588 | } |
| 1589 | } |
| 1590 | |
| 1591 | /******************************************************************************* |
| 1592 | * CONFIGURE DDR REGISTERS |
| 1593 | ******************************************************************************/ |
| 1594 | static void ddr_config_sub(void) |
| 1595 | { |
| 1596 | int32_t i; |
| 1597 | uint32_t ch, slice; |
| 1598 | uint32_t dataL; |
| 1599 | uint32_t tmp; |
| 1600 | uint8_t high_byte[SLICE_CNT]; |
| 1601 | foreach_vch(ch) { |
| 1602 | /*********************************************************************** |
| 1603 | BOARD SETTINGS (DQ,DM,VREF_DRIVING) |
| 1604 | ***********************************************************************/ |
| 1605 | for (slice = 0; slice < SLICE_CNT; slice++) { |
| 1606 | high_byte[slice] = |
| 1607 | (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) % 2; |
| 1608 | ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0, |
| 1609 | Boardcnf->ch[ch].dq_swap[slice]); |
| 1610 | ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1, |
| 1611 | Boardcnf->ch[ch].dm_swap[slice]); |
| 1612 | if (high_byte[slice]) { |
| 1613 | /* HIGHER 16 BYTE */ |
| 1614 | ddr_setval_s(ch, slice, |
| 1615 | _reg_PHY_CALVL_VREF_DRIVING_SLICE, |
| 1616 | 0x00); |
| 1617 | } else { |
| 1618 | /* LOWER 16 BYTE */ |
| 1619 | ddr_setval_s(ch, slice, |
| 1620 | _reg_PHY_CALVL_VREF_DRIVING_SLICE, |
| 1621 | 0x01); |
| 1622 | } |
| 1623 | } |
| 1624 | |
| 1625 | /*********************************************************************** |
| 1626 | BOARD SETTINGS (CA,ADDR_SEL) |
| 1627 | ***********************************************************************/ |
| 1628 | const uint32_t _par_CALVL_DEVICE_MAP = 1; |
| 1629 | dataL = Boardcnf->ch[ch].ca_swap | 0x00888888; |
| 1630 | |
| 1631 | /* --- ADR_CALVL_SWIZZLE --- */ |
| 1632 | if (Prr_Product == PRR_PRODUCT_M3) { |
| 1633 | ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL); |
| 1634 | ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, |
| 1635 | 0x00000000); |
| 1636 | ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, dataL); |
| 1637 | ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, |
| 1638 | 0x00000000); |
| 1639 | ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, |
| 1640 | _par_CALVL_DEVICE_MAP); |
| 1641 | } else { |
| 1642 | ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, dataL); |
| 1643 | ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000); |
| 1644 | ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP, |
| 1645 | _par_CALVL_DEVICE_MAP); |
| 1646 | } |
| 1647 | |
| 1648 | /* --- ADR_ADDR_SEL --- */ |
| 1649 | if ((Prr_Product == PRR_PRODUCT_H3) |
| 1650 | && (Prr_Cut > PRR_PRODUCT_11)) { |
| 1651 | dataL = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap; |
| 1652 | } else { |
| 1653 | dataL = 0; |
| 1654 | tmp = Boardcnf->ch[ch].ca_swap; |
| 1655 | for (i = 0; i < 6; i++) { |
| 1656 | dataL |= ((tmp & 0x0f) << (i * 5)); |
| 1657 | tmp = tmp >> 4; |
| 1658 | } |
| 1659 | } |
| 1660 | ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, dataL); |
| 1661 | |
| 1662 | /*********************************************************************** |
| 1663 | BOARD SETTINGS (BYTE_ORDER_SEL) |
| 1664 | ***********************************************************************/ |
| 1665 | if (Prr_Product == PRR_PRODUCT_M3) { |
| 1666 | /* --- DATA_BYTE_SWAP --- */ |
| 1667 | dataL = 0; |
| 1668 | tmp = Boardcnf->ch[ch].dqs_swap; |
| 1669 | for (i = 0; i < 4; i++) { |
| 1670 | dataL |= ((tmp & 0x03) << (i * 2)); |
| 1671 | tmp = tmp >> 4; |
| 1672 | } |
| 1673 | } else { |
| 1674 | /* --- DATA_BYTE_SWAP --- */ |
| 1675 | dataL = Boardcnf->ch[ch].dqs_swap; |
| 1676 | ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01); |
| 1677 | ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0, |
| 1678 | (dataL) & 0x0f); |
| 1679 | ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1, |
| 1680 | (dataL >> 4 * 1) & 0x0f); |
| 1681 | ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2, |
| 1682 | (dataL >> 4 * 2) & 0x0f); |
| 1683 | ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3, |
| 1684 | (dataL >> 4 * 3) & 0x0f); |
| 1685 | |
| 1686 | ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00); |
| 1687 | } |
| 1688 | ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, dataL); |
| 1689 | } |
| 1690 | } |
| 1691 | |
| 1692 | static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t * p_swz) |
| 1693 | { |
| 1694 | uint32_t slice; |
| 1695 | uint32_t tmp; |
| 1696 | uint32_t tgt; |
| 1697 | if (ddr_csn / 2) { |
| 1698 | tgt = 3; |
| 1699 | } else { |
| 1700 | tgt = 1; |
| 1701 | } |
| 1702 | |
| 1703 | for (slice = 0; slice < SLICE_CNT; slice++) { |
| 1704 | tmp = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; |
| 1705 | if (tgt == tmp) |
| 1706 | break; |
| 1707 | } |
| 1708 | tmp = Boardcnf->ch[ch].ca_swap; |
| 1709 | if (slice % 2) |
| 1710 | tmp |= 0x00888888; |
| 1711 | *p_swz = tmp; |
| 1712 | } |
| 1713 | |
| 1714 | static void ddr_config_sub_h3v1x(void) |
| 1715 | { |
| 1716 | uint32_t ch, slice; |
| 1717 | uint32_t dataL; |
| 1718 | uint32_t tmp; |
| 1719 | uint8_t high_byte[SLICE_CNT]; |
| 1720 | |
| 1721 | foreach_vch(ch) { |
| 1722 | uint32_t ca_swizzle; |
| 1723 | uint32_t ca; |
| 1724 | uint32_t csmap; |
| 1725 | /*********************************************************************** |
| 1726 | BOARD SETTINGS (DQ,DM,VREF_DRIVING) |
| 1727 | ***********************************************************************/ |
| 1728 | csmap = 0; |
| 1729 | for (slice = 0; slice < SLICE_CNT; slice++) { |
| 1730 | tmp = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; |
| 1731 | high_byte[slice] = tmp % 2; |
| 1732 | if (tmp == 1 && (slice >= 2)) |
| 1733 | csmap |= 0x05; |
| 1734 | if (tmp == 3 && (slice >= 2)) |
| 1735 | csmap |= 0x50; |
| 1736 | ddr_setval_s(ch, slice, _reg_PHY_DQ_SWIZZLING, |
| 1737 | Boardcnf->ch[ch].dq_swap[slice]); |
| 1738 | if (high_byte[slice]) { |
| 1739 | /* HIGHER 16 BYTE */ |
| 1740 | ddr_setval_s(ch, slice, |
| 1741 | _reg_PHY_CALVL_VREF_DRIVING_SLICE, |
| 1742 | 0x00); |
| 1743 | } else { |
| 1744 | /* LOWER 16 BYTE */ |
| 1745 | ddr_setval_s(ch, slice, |
| 1746 | _reg_PHY_CALVL_VREF_DRIVING_SLICE, |
| 1747 | 0x01); |
| 1748 | } |
| 1749 | } |
| 1750 | /*********************************************************************** |
| 1751 | BOARD SETTINGS (CA,ADDR_SEL) |
| 1752 | ***********************************************************************/ |
| 1753 | ca = Boardcnf->ch[ch].ca_swap; |
| 1754 | ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca); |
| 1755 | ddr_setval(ch, _reg_PHY_CALVL_CS_MAP, csmap); |
| 1756 | |
| 1757 | get_ca_swizzle(ch, 0, &ca_swizzle); |
| 1758 | |
| 1759 | ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, ca_swizzle); |
| 1760 | ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000); |
| 1761 | ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, 0x00000000); |
| 1762 | ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000); |
| 1763 | ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, 0x01); |
| 1764 | |
| 1765 | for (slice = 0; slice < SLICE_CNT; slice++) { |
| 1766 | const uint8_t o_mr15 = 0x55; |
| 1767 | const uint8_t o_mr20 = 0x55; |
| 1768 | const uint16_t o_mr32_mr40 = 0x5a3c; |
| 1769 | uint32_t o_inv; |
| 1770 | uint32_t inv; |
| 1771 | uint32_t bit_soc; |
| 1772 | uint32_t bit_mem; |
| 1773 | uint32_t j; |
| 1774 | |
| 1775 | ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_NUM, |
| 1776 | 0x01); |
| 1777 | ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_START, |
| 1778 | 0x08); |
| 1779 | |
| 1780 | if (high_byte[slice]) |
| 1781 | o_inv = o_mr20; |
| 1782 | else |
| 1783 | o_inv = o_mr15; |
| 1784 | |
| 1785 | tmp = Boardcnf->ch[ch].dq_swap[slice]; |
| 1786 | inv = 0; |
| 1787 | j = 0; |
| 1788 | for (bit_soc = 0; bit_soc < 8; bit_soc++) { |
| 1789 | bit_mem = (tmp >> (4 * bit_soc)) & 0x0f; |
| 1790 | j |= (1U << bit_mem); |
| 1791 | if (o_inv & (1U << bit_mem)) |
| 1792 | inv |= (1U << bit_soc); |
| 1793 | } |
| 1794 | dataL = o_mr32_mr40; |
| 1795 | if (!high_byte[slice]) |
| 1796 | dataL |= (inv << 24); |
| 1797 | if (high_byte[slice]) |
| 1798 | dataL |= (inv << 16); |
| 1799 | ddr_setval_s(ch, slice, _reg_PHY_LP4_RDLVL_PATT8, |
| 1800 | dataL); |
| 1801 | } |
| 1802 | } |
| 1803 | } |
| 1804 | |
| 1805 | static void ddr_config(void) |
| 1806 | { |
| 1807 | int32_t i; |
| 1808 | uint32_t ch, slice; |
| 1809 | uint32_t dataL; |
| 1810 | uint32_t tmp; |
| 1811 | |
| 1812 | /*********************************************************************** |
| 1813 | configure ddrphy registers |
| 1814 | ***********************************************************************/ |
| 1815 | if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { |
| 1816 | ddr_config_sub_h3v1x(); |
| 1817 | } else { |
| 1818 | ddr_config_sub(); /* H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */ |
| 1819 | } |
| 1820 | |
| 1821 | /*********************************************************************** |
| 1822 | WDQ_USER_PATT |
| 1823 | ***********************************************************************/ |
| 1824 | foreach_vch(ch) { |
| 1825 | union { |
| 1826 | uint32_t ui32[4]; |
| 1827 | uint8_t ui8[16]; |
| 1828 | } patt; |
| 1829 | uint16_t patm; |
| 1830 | for (slice = 0; slice < SLICE_CNT; slice++) { |
| 1831 | patm = 0; |
| 1832 | for (i = 0; i < 16; i++) { |
| 1833 | tmp = Boardcnf->ch[ch].wdqlvl_patt[i]; |
| 1834 | patt.ui8[i] = tmp & 0xff; |
| 1835 | if (tmp & 0x100) |
| 1836 | patm |= (1U << i); |
| 1837 | } |
| 1838 | ddr_setval_s(ch, slice, _reg_PHY_USER_PATT0, |
| 1839 | patt.ui32[0]); |
| 1840 | ddr_setval_s(ch, slice, _reg_PHY_USER_PATT1, |
| 1841 | patt.ui32[1]); |
| 1842 | ddr_setval_s(ch, slice, _reg_PHY_USER_PATT2, |
| 1843 | patt.ui32[2]); |
| 1844 | ddr_setval_s(ch, slice, _reg_PHY_USER_PATT3, |
| 1845 | patt.ui32[3]); |
| 1846 | ddr_setval_s(ch, slice, _reg_PHY_USER_PATT4, patm); |
| 1847 | } |
| 1848 | } |
| 1849 | |
| 1850 | /*********************************************************************** |
| 1851 | CACS DLY |
| 1852 | ***********************************************************************/ |
| 1853 | dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj); |
| 1854 | set_dfifrequency(0x1f); |
| 1855 | foreach_vch(ch) { |
| 1856 | int16_t adj; |
| 1857 | for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { |
| 1858 | adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]); |
| 1859 | ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], |
| 1860 | dataL + adj); |
| 1861 | } |
| 1862 | } |
| 1863 | set_dfifrequency(0x00); |
| 1864 | |
| 1865 | /*********************************************************************** |
| 1866 | WDQDM DLY |
| 1867 | ***********************************************************************/ |
| 1868 | dataL = Boardcnf->dqdm_dly_w; |
| 1869 | foreach_vch(ch) { |
| 1870 | int8_t _adj; |
| 1871 | int16_t adj; |
| 1872 | uint32_t dq; |
| 1873 | for (slice = 0; slice < SLICE_CNT; slice++) { |
| 1874 | for (i = 0; i <= 8; i++) { |
| 1875 | dq = slice * 8 + i; |
| 1876 | if (i == 8) |
| 1877 | _adj = Boardcnf->ch[ch].dm_adj_w[slice]; |
| 1878 | else |
| 1879 | _adj = Boardcnf->ch[ch].dq_adj_w[dq]; |
| 1880 | adj = _f_scale_adj(_adj); |
| 1881 | ddr_setval_s(ch, slice, |
| 1882 | _reg_PHY_CLK_WRX_SLAVE_DELAY[i], |
| 1883 | dataL + adj); |
| 1884 | } |
| 1885 | } |
| 1886 | } |
| 1887 | |
| 1888 | /*********************************************************************** |
| 1889 | RDQDM DLY |
| 1890 | ***********************************************************************/ |
| 1891 | dataL = Boardcnf->dqdm_dly_r; |
| 1892 | foreach_vch(ch) { |
| 1893 | int8_t _adj; |
| 1894 | int16_t adj; |
| 1895 | uint32_t dq; |
| 1896 | for (slice = 0; slice < SLICE_CNT; slice++) { |
| 1897 | for (i = 0; i <= 8; i++) { |
| 1898 | dq = slice * 8 + i; |
| 1899 | if (i == 8) |
| 1900 | _adj = Boardcnf->ch[ch].dm_adj_r[slice]; |
| 1901 | else |
| 1902 | _adj = Boardcnf->ch[ch].dq_adj_r[dq]; |
| 1903 | adj = _f_scale_adj(_adj); |
| 1904 | ddr_setval_s(ch, slice, |
| 1905 | _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY |
| 1906 | [i], dataL + adj); |
| 1907 | ddr_setval_s(ch, slice, |
| 1908 | _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY |
| 1909 | [i], dataL + adj); |
| 1910 | } |
| 1911 | } |
| 1912 | } |
| 1913 | } |
| 1914 | |
| 1915 | /******************************************************************************* |
| 1916 | * DBSC register setting functions |
| 1917 | ******************************************************************************/ |
| 1918 | static void dbsc_regset_pre(void) |
| 1919 | { |
| 1920 | uint32_t ch, csab; |
| 1921 | uint32_t dataL; |
| 1922 | |
| 1923 | /*********************************************************************** |
| 1924 | PRIMARY SETTINGS |
| 1925 | ***********************************************************************/ |
| 1926 | /* LPDDR4, BL=16, DFI interface */ |
| 1927 | mmio_write_32(DBSC_DBKIND, 0x0000000a); |
| 1928 | mmio_write_32(DBSC_DBBL, 0x00000002); |
| 1929 | mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); |
| 1930 | |
| 1931 | /* FREQRATIO=2 */ |
| 1932 | mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); |
| 1933 | |
| 1934 | /* Chanel map (H3 Ver.1.x) */ |
| 1935 | if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) |
| 1936 | mmio_write_32(DBSC_DBSCHCNT1, 0x00001010); |
| 1937 | |
| 1938 | /* DRAM SIZE REGISTER: |
| 1939 | * set all ranks as density=0(4Gb) for PHY initialization |
| 1940 | */ |
| 1941 | foreach_vch(ch) |
| 1942 | for (csab = 0; csab < 4; csab++) |
| 1943 | mmio_write_32(DBSC_DBMEMCONF(ch, csab), DBMEMCONF_REGD(0)); |
| 1944 | |
| 1945 | if (Prr_Product == PRR_PRODUCT_M3) { |
| 1946 | dataL = 0xe4e4e4e4; |
| 1947 | foreach_ech(ch) { |
| 1948 | if ((ddr_phyvalid & (1U << ch))) |
| 1949 | dataL = (dataL & (~(0x000000FF << (ch * 8)))) |
| 1950 | | (((Boardcnf->ch[ch].dqs_swap & 0x0003) |
| 1951 | | ((Boardcnf->ch[ch].dqs_swap & 0x0030) |
| 1952 | >> 2) |
| 1953 | | ((Boardcnf->ch[ch].dqs_swap & 0x0300) |
| 1954 | >> 4) |
| 1955 | | ((Boardcnf->ch[ch].dqs_swap & 0x3000) |
| 1956 | >> 6)) << (ch * 8)); |
| 1957 | } |
| 1958 | mmio_write_32(DBSC_DBBSWAP, dataL); |
| 1959 | } |
| 1960 | } |
| 1961 | |
| 1962 | static void dbsc_regset(void) |
| 1963 | { |
| 1964 | int32_t i; |
| 1965 | uint32_t ch; |
| 1966 | uint32_t dataL; |
| 1967 | uint32_t tmp[4]; |
| 1968 | |
| 1969 | /* RFC */ |
| 1970 | if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_20) |
| 1971 | && (max_density == 0)) { |
| 1972 | js2[JS2_tRFCpb] = |
| 1973 | _f_scale(ddr_mbps, ddr_mbpsdiv, |
| 1974 | 1UL * jedec_spec2_tRFC_pb_ab[0][1] * 1000, 0); |
| 1975 | js2[JS2_tRFCab] = |
| 1976 | _f_scale(ddr_mbps, ddr_mbpsdiv, |
| 1977 | 1UL * jedec_spec2_tRFC_pb_ab[1][1] * 1000, 0); |
| 1978 | } else { |
| 1979 | js2[JS2_tRFCpb] = _f_scale(ddr_mbps, ddr_mbpsdiv, |
| 1980 | 1UL * |
| 1981 | jedec_spec2_tRFC_pb_ab[0] |
| 1982 | [max_density] * 1000, 0); |
| 1983 | js2[JS2_tRFCab] = |
| 1984 | _f_scale(ddr_mbps, ddr_mbpsdiv, |
| 1985 | 1UL * jedec_spec2_tRFC_pb_ab[1][max_density] * |
| 1986 | 1000, 0); |
| 1987 | } |
| 1988 | |
| 1989 | /* DBTR0.CL : RL */ |
| 1990 | mmio_write_32(DBSC_DBTR(0), RL); |
| 1991 | |
| 1992 | /* DBTR1.CWL : WL */ |
| 1993 | mmio_write_32(DBSC_DBTR(1), WL); |
| 1994 | |
| 1995 | /* DBTR2.AL : 0 */ |
| 1996 | mmio_write_32(DBSC_DBTR(2), 0); |
| 1997 | |
| 1998 | /* DBTR3.TRCD: tRCD */ |
| 1999 | mmio_write_32(DBSC_DBTR(3), js2[JS2_tRCD]); |
| 2000 | |
| 2001 | /* DBTR4.TRPA,TRP: tRPab,tRPpb */ |
| 2002 | mmio_write_32(DBSC_DBTR(4), (js2[JS2_tRPab] << 16) | js2[JS2_tRPpb]); |
| 2003 | |
| 2004 | /* DBTR5.TRC : use tRCpb */ |
| 2005 | mmio_write_32(DBSC_DBTR(5), js2[JS2_tRCpb]); |
| 2006 | |
| 2007 | /* DBTR6.TRAS : tRAS */ |
| 2008 | mmio_write_32(DBSC_DBTR(6), js2[JS2_tRAS]); |
| 2009 | |
| 2010 | /* DBTR7.TRRD : tRRD */ |
| 2011 | mmio_write_32(DBSC_DBTR(7), (js2[JS2_tRRD] << 16) | js2[JS2_tRRD]); |
| 2012 | |
| 2013 | /* DBTR8.TFAW : tFAW */ |
| 2014 | mmio_write_32(DBSC_DBTR(8), js2[JS2_tFAW]); |
| 2015 | |
| 2016 | /* DBTR9.TRDPR : tRTP */ |
| 2017 | mmio_write_32(DBSC_DBTR(9), js2[JS2_tRTP]); |
| 2018 | |
| 2019 | /* DBTR10.TWR : nWR */ |
| 2020 | mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nWR); |
| 2021 | |
| 2022 | /* DBTR11.TRDWR : RL + tDQSCK + BL/2 + Rounddown(tRPST) - WL + tWPRE */ |
| 2023 | mmio_write_32(DBSC_DBTR(11), |
| 2024 | RL + js2[JS2_tDQSCK] + (16 / 2) + 1 - WL + 2 + 2); |
| 2025 | |
| 2026 | /* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */ |
| 2027 | dataL = WL + 1 + (16 / 2) + js2[JS2_tWTR]; |
| 2028 | mmio_write_32(DBSC_DBTR(12), (dataL << 16) | dataL); |
| 2029 | |
| 2030 | /* DBTR13.TRFCPB,TRFCAB : tRFCpb, tRFCab */ |
| 2031 | mmio_write_32(DBSC_DBTR(13), (js2[JS2_tRFCab])); |
| 2032 | |
| 2033 | /* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */ |
| 2034 | mmio_write_32(DBSC_DBTR(14), |
| 2035 | (js2[JS2_tCKEHCMD] << 16) | (js2[JS2_tCKEHCMD])); |
| 2036 | |
| 2037 | /* DBTR15.TCKESR,TCKEL : tSR,tCKELPD */ |
| 2038 | mmio_write_32(DBSC_DBTR(15), (js2[JS2_tSR] << 16) | (js2[JS2_tCKELPD])); |
| 2039 | |
| 2040 | /* DBTR16 */ |
| 2041 | /* WDQL : tphy_wrlat + tphy_wrdata */ |
| 2042 | tmp[0] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1); |
| 2043 | /* DQENLTNCY : tphy_wrlat = WL-2 */ |
| 2044 | tmp[1] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1); |
| 2045 | /* DQL : tphy_rdlat + trdata_en */ |
| 2046 | /* it is not important for dbsc */ |
| 2047 | tmp[2] = RL + 16; |
| 2048 | /* DQIENLTNCY : trdata_en */ |
| 2049 | tmp[3] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1) - 1; |
| 2050 | mmio_write_32(DBSC_DBTR(16), |
| 2051 | (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); |
| 2052 | |
| 2053 | /* DBTR24 */ |
| 2054 | /* WRCSLAT = WRLAT -5 */ |
| 2055 | tmp[0] -= 5; |
| 2056 | /* WRCSGAP = 5 */ |
| 2057 | tmp[1] = 5; |
| 2058 | /* RDCSLAT = RDLAT_ADJ +2 */ |
| 2059 | tmp[2] = tmp[3] + 2; |
| 2060 | /* RDCSGAP = 6 */ |
| 2061 | if (Prr_Product == PRR_PRODUCT_M3) { |
| 2062 | tmp[3] = 4; |
| 2063 | } else { |
| 2064 | tmp[3] = 6; |
| 2065 | } |
| 2066 | mmio_write_32(DBSC_DBTR(24), |
| 2067 | (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); |
| 2068 | |
| 2069 | /* DBTR17.TMODRD,TMOD,TRDMR: tMRR,tMRD,(0) */ |
| 2070 | mmio_write_32(DBSC_DBTR(17), |
| 2071 | (js2[JS2_tMRR] << 24) | (js2[JS2_tMRD] << 16)); |
| 2072 | |
| 2073 | /* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */ |
| 2074 | mmio_write_32(DBSC_DBTR(18), 0); |
| 2075 | |
| 2076 | /* DBTR19.TZQCL, TZQCS : do not use in LPDDR4 */ |
| 2077 | mmio_write_32(DBSC_DBTR(19), 0); |
| 2078 | |
| 2079 | /* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */ |
| 2080 | dataL = js2[JS2_tRFCab] + js2[JS2_tCKEHCMD]; |
| 2081 | mmio_write_32(DBSC_DBTR(20), (dataL << 16) | dataL); |
| 2082 | |
| 2083 | /* DBTR21.TCCD */ |
| 2084 | /* DBTR23.TCCD */ |
| 2085 | /* H3 Ver.1.0 cannot use TBTR23 feature */ |
| 2086 | if (ddr_tccd == 8 && |
| 2087 | !((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_10)) |
| 2088 | ) { |
| 2089 | dataL = 8; |
| 2090 | mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL); |
| 2091 | mmio_write_32(DBSC_DBTR(23), 0x00000002); |
| 2092 | } else if (ddr_tccd <= 11) { |
| 2093 | dataL = 11; |
| 2094 | mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL); |
| 2095 | mmio_write_32(DBSC_DBTR(23), 0x00000000); |
| 2096 | } else { |
| 2097 | dataL = ddr_tccd; |
| 2098 | mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL); |
| 2099 | mmio_write_32(DBSC_DBTR(23), 0x00000000); |
| 2100 | } |
| 2101 | |
| 2102 | /* DBTR22.ZQLAT : */ |
| 2103 | dataL = js2[JS2_tZQCALns] * 100; /* 1000 * 1000 ps */ |
| 2104 | dataL = (dataL << 16) | (js2[JS2_tZQLAT] + 24 + 20); |
| 2105 | mmio_write_32(DBSC_DBTR(22), dataL); |
| 2106 | |
| 2107 | /* DBTR25 : do not use in LPDDR4 */ |
| 2108 | mmio_write_32(DBSC_DBTR(25), 0); |
| 2109 | |
| 2110 | /* DBRNK : */ |
| 2111 | /* |
| 2112 | * DBSC_DBRNK2 rkrr |
| 2113 | * DBSC_DBRNK3 rkrw |
| 2114 | * DBSC_DBRNK4 rkwr |
| 2115 | * DBSC_DBRNK5 rkww |
| 2116 | */ |
| 2117 | #define _par_DBRNK_VAL (0x7007) |
| 2118 | |
| 2119 | for (i = 0; i < 4; i++) { |
| 2120 | uint32_t dataL2; |
| 2121 | dataL = (_par_DBRNK_VAL >> (i * 4)) & 0x0f; |
| 2122 | if ((Prr_Product == PRR_PRODUCT_H3) |
| 2123 | && (Prr_Cut > PRR_PRODUCT_11) && (i == 0)) { |
| 2124 | dataL += 1; |
| 2125 | } |
| 2126 | dataL2 = 0; |
| 2127 | foreach_vch(ch) { |
| 2128 | dataL2 = dataL2 | (dataL << (4 * ch)); |
| 2129 | } |
| 2130 | mmio_write_32(DBSC_DBRNK(2 + i), dataL2); |
| 2131 | } |
| 2132 | mmio_write_32(DBSC_DBADJ0, 0x00000000); |
| 2133 | |
| 2134 | /*********************************************************************** |
| 2135 | timing registers for Scheduler |
| 2136 | ***********************************************************************/ |
| 2137 | /* SCFCTST0 */ |
| 2138 | /* SCFCTST0 ACT-ACT */ |
| 2139 | tmp[3] = 1UL * js2[JS2_tRCpb] * 800 * ddr_mbpsdiv / ddr_mbps; |
| 2140 | /* SCFCTST0 RDA-ACT */ |
| 2141 | tmp[2] = |
| 2142 | 1UL * ((16 / 2) + js2[JS2_tRTP] - 8 + |
| 2143 | js2[JS2_tRPpb]) * 800 * ddr_mbpsdiv / ddr_mbps; |
| 2144 | /* SCFCTST0 WRA-ACT */ |
| 2145 | tmp[1] = |
| 2146 | 1UL * (WL + 1 + (16 / 2) + |
| 2147 | js1[js1_ind].nWR) * 800 * ddr_mbpsdiv / ddr_mbps; |
| 2148 | /* SCFCTST0 PRE-ACT */ |
| 2149 | tmp[0] = 1UL * js2[JS2_tRPpb]; |
| 2150 | mmio_write_32(DBSC_SCFCTST0, |
| 2151 | (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); |
| 2152 | |
| 2153 | /* SCFCTST1 */ |
| 2154 | /* SCFCTST1 RD-WR */ |
| 2155 | tmp[3] = |
| 2156 | 1UL * (mmio_read_32(DBSC_DBTR(11)) & 0xff) * 800 * ddr_mbpsdiv / |
| 2157 | ddr_mbps; |
| 2158 | /* SCFCTST1 WR-RD */ |
| 2159 | tmp[2] = |
| 2160 | 1UL * (mmio_read_32(DBSC_DBTR(12)) & 0xff) * 800 * ddr_mbpsdiv / |
| 2161 | ddr_mbps; |
| 2162 | /* SCFCTST1 ACT-RD/WR */ |
| 2163 | tmp[1] = 1UL * js2[JS2_tRCD] * 800 * ddr_mbpsdiv / ddr_mbps; |
| 2164 | /* SCFCTST1 ASYNCOFS */ |
| 2165 | tmp[0] = 12; |
| 2166 | mmio_write_32(DBSC_SCFCTST1, |
| 2167 | (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); |
| 2168 | |
| 2169 | /* DBSCHRW1 */ |
| 2170 | /* DBSCHRW1 SCTRFCAB */ |
| 2171 | tmp[0] = 1UL * js2[JS2_tRFCab] * 800 * ddr_mbpsdiv / ddr_mbps; |
| 2172 | dataL = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16) |
| 2173 | + (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) |
| 2174 | + (0x28 * 2)) * 400 * 2 * ddr_mbpsdiv / ddr_mbps + 7; |
| 2175 | if (tmp[0] < dataL) |
| 2176 | tmp[0] = dataL; |
| 2177 | mmio_write_32(DBSC_DBSCHRW1, tmp[0]); |
| 2178 | |
| 2179 | /*********************************************************************** |
| 2180 | QOS and CAM |
| 2181 | ***********************************************************************/ |
| 2182 | #ifdef ddr_qos_init_setting /* only for non qos_init */ |
| 2183 | /*wbkwait(0004), wbkmdhi(4,2),wbkmdlo(1,8) */ |
| 2184 | mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); |
| 2185 | /*0(fillunit),8(dirtymax),4(dirtymin) */ |
| 2186 | mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4); |
| 2187 | /*stop_tolerance */ |
| 2188 | mmio_write_32(DBSC_DBSCHRW0, 0x22421111); |
| 2189 | /*rd-wr/wr-rd toggle priority */ |
| 2190 | mmio_write_32(DBSC_SCFCTST2, 0x012F1123); |
| 2191 | mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); |
| 2192 | mmio_write_32(DBSC_DBSCHCNT0, 0x000F0037); |
| 2193 | |
| 2194 | /* QoS Settings */ |
| 2195 | mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00U); |
| 2196 | mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00U); |
| 2197 | mmio_write_32(DBSC_DBSCHQOS02, 0x00000000U); |
| 2198 | mmio_write_32(DBSC_DBSCHQOS03, 0x00000000U); |
| 2199 | mmio_write_32(DBSC_DBSCHQOS40, 0x00000300U); |
| 2200 | mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0U); |
| 2201 | mmio_write_32(DBSC_DBSCHQOS42, 0x00000200U); |
| 2202 | mmio_write_32(DBSC_DBSCHQOS43, 0x00000100U); |
| 2203 | mmio_write_32(DBSC_DBSCHQOS90, 0x00000100U); |
| 2204 | mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0U); |
| 2205 | mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0U); |
| 2206 | mmio_write_32(DBSC_DBSCHQOS93, 0x00000040U); |
| 2207 | mmio_write_32(DBSC_DBSCHQOS120, 0x00000040U); |
| 2208 | mmio_write_32(DBSC_DBSCHQOS121, 0x00000030U); |
| 2209 | mmio_write_32(DBSC_DBSCHQOS122, 0x00000020U); |
| 2210 | mmio_write_32(DBSC_DBSCHQOS123, 0x00000010U); |
| 2211 | mmio_write_32(DBSC_DBSCHQOS130, 0x00000100U); |
| 2212 | mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0U); |
| 2213 | mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0U); |
| 2214 | mmio_write_32(DBSC_DBSCHQOS133, 0x00000040U); |
| 2215 | mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0U); |
| 2216 | mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0U); |
| 2217 | mmio_write_32(DBSC_DBSCHQOS142, 0x00000080U); |
| 2218 | mmio_write_32(DBSC_DBSCHQOS143, 0x00000040U); |
| 2219 | mmio_write_32(DBSC_DBSCHQOS150, 0x00000040U); |
| 2220 | mmio_write_32(DBSC_DBSCHQOS151, 0x00000030U); |
| 2221 | mmio_write_32(DBSC_DBSCHQOS152, 0x00000020U); |
| 2222 | mmio_write_32(DBSC_DBSCHQOS153, 0x00000010U); |
| 2223 | |
| 2224 | mmio_write_32(QOSCTRL_RAEN, 0x00000001U); |
| 2225 | #endif /* ddr_qos_init_setting */ |
| 2226 | /* H3 Ver.1.1 need to set monitor function */ |
| 2227 | if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_11)) { |
| 2228 | mmio_write_32(DBSC_DBMONCONF4, 0x00700000); |
| 2229 | } |
| 2230 | |
| 2231 | if (Prr_Product == PRR_PRODUCT_H3) { |
| 2232 | if (Prr_Cut == PRR_PRODUCT_10) { |
| 2233 | /* resrdis, simple mode, sc off */ |
| 2234 | mmio_write_32(DBSC_DBBCAMDIS, 0x00000007); |
| 2235 | } else if (Prr_Cut == PRR_PRODUCT_11) { |
| 2236 | /* resrdis, simple mode */ |
| 2237 | mmio_write_32(DBSC_DBBCAMDIS, 0x00000005); |
| 2238 | } else if (Prr_Cut < PRR_PRODUCT_30) { |
| 2239 | /* H3 Ver.2.0 */ |
| 2240 | /* resrdis */ |
| 2241 | mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); |
| 2242 | } else { /* H3 Ver.3.0(include H3N) */ |
| 2243 | /* exprespque */ |
| 2244 | mmio_write_32(DBSC_DBBCAMDIS, 0x00000010); |
| 2245 | } |
| 2246 | } else { /* M3-W/M3-N/V3H */ |
| 2247 | /* resrdis */ |
| 2248 | mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); |
| 2249 | } |
| 2250 | } |
| 2251 | |
| 2252 | static void dbsc_regset_post(void) |
| 2253 | { |
| 2254 | uint32_t ch, cs; |
| 2255 | uint32_t dataL; |
| 2256 | uint32_t slice, rdlat_max, rdlat_min; |
| 2257 | |
| 2258 | rdlat_max = 0; |
| 2259 | rdlat_min = 0xffff; |
| 2260 | foreach_vch(ch) { |
| 2261 | for (cs = 0; cs < CS_CNT; cs++) { |
| 2262 | if ((ch_have_this_cs[cs] & (1U << ch)) != 0) { |
| 2263 | for (slice = 0; slice < SLICE_CNT; slice++) { |
| 2264 | ddr_setval_s(ch, slice, |
| 2265 | _reg_PHY_PER_CS_TRAINING_INDEX, |
| 2266 | cs); |
| 2267 | dataL = |
| 2268 | ddr_getval_s(ch, slice, |
| 2269 | _reg_PHY_RDDQS_LATENCY_ADJUST); |
| 2270 | if (dataL > rdlat_max) |
| 2271 | rdlat_max = dataL; |
| 2272 | if (dataL < rdlat_min) |
| 2273 | rdlat_min = dataL; |
| 2274 | } |
| 2275 | } |
| 2276 | } |
| 2277 | } |
| 2278 | if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) { |
| 2279 | mmio_write_32(DBSC_DBTR(24), |
| 2280 | ((rdlat_max * 2 - rdlat_min + 4) << 24) + |
| 2281 | ((rdlat_min + 2) << 16) + |
| 2282 | mmio_read_32(DBSC_DBTR(24))); |
| 2283 | } else { |
| 2284 | mmio_write_32(DBSC_DBTR(24), |
| 2285 | ((rdlat_max + 2) << 24) + |
| 2286 | ((rdlat_max + 2) << 16) + |
| 2287 | mmio_read_32(DBSC_DBTR(24))); |
| 2288 | } |
| 2289 | |
| 2290 | /* set ddr density information */ |
| 2291 | foreach_ech(ch) { |
| 2292 | for (cs = 0; cs < CS_CNT; cs++) { |
| 2293 | if (ddr_density[ch][cs] == 0xff) { |
| 2294 | mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00); |
| 2295 | } else { |
| 2296 | mmio_write_32(DBSC_DBMEMCONF(ch, cs), |
| 2297 | DBMEMCONF_REGD(ddr_density[ch] |
| 2298 | [cs])); |
| 2299 | } |
| 2300 | } |
| 2301 | mmio_write_32(DBSC_DBMEMCONF(ch, 2), 0x00000000); |
| 2302 | mmio_write_32(DBSC_DBMEMCONF(ch, 3), 0x00000000); |
| 2303 | } |
| 2304 | |
| 2305 | mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); |
| 2306 | |
| 2307 | /*set DBI */ |
| 2308 | if (Boardcnf->dbi_en) |
| 2309 | mmio_write_32(DBSC_DBDBICNT, 0x00000003); |
| 2310 | |
| 2311 | /* H3 Ver.2.0 or later/M3-N/V3H DBI wa */ |
| 2312 | if ((((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) |
| 2313 | || (Prr_Product == PRR_PRODUCT_M3N) |
| 2314 | || (Prr_Product == PRR_PRODUCT_V3H)) && (Boardcnf->dbi_en)) |
| 2315 | reg_ddrphy_write_a(0x00001010, 0x01000000); |
| 2316 | |
| 2317 | /*set REFCYCLE */ |
| 2318 | dataL = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv; |
| 2319 | mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (dataL & 0x0000ffff)); |
| 2320 | mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS); |
| 2321 | #if RCAR_REWT_TRAINING != 0 |
| 2322 | /* Periodic-WriteDQ Training seeting */ |
| 2323 | if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) |
| 2324 | || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut == PRR_PRODUCT_10))) { |
| 2325 | /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */ |
| 2326 | } else { |
| 2327 | /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H -> Periodic-WriteDQ Training seeting */ |
| 2328 | |
| 2329 | /* Periodic WriteDQ Training seeting */ |
| 2330 | mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000); |
| 2331 | |
| 2332 | ddr_setval_ach_as(_reg_PHY_WDQLVL_PATT, 0x04); |
| 2333 | ddr_setval_ach_as(_reg_PHY_WDQLVL_QTR_DLY_STEP, 0x0F); |
| 2334 | ddr_setval_ach_as(_reg_PHY_WDQLVL_DLY_STEP, 0x50); |
| 2335 | ddr_setval_ach_as(_reg_PHY_WDQLVL_DQDM_SLV_DLY_START, 0x0300); |
| 2336 | |
| 2337 | ddr_setval_ach(_reg_PI_WDQLVL_CS_MAP, |
| 2338 | ddrtbl_getval(_cnf_DDR_PI_REGSET, |
| 2339 | _reg_PI_WDQLVL_CS_MAP)); |
| 2340 | ddr_setval_ach(_reg_PI_LONG_COUNT_MASK, 0x1f); |
| 2341 | ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00); |
| 2342 | ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100); |
| 2343 | ddr_setval_ach(_reg_PI_WDQLVL_ROTATE, 0x01); |
| 2344 | ddr_setval_ach(_reg_PI_TREF_F0, 0x0000); |
| 2345 | ddr_setval_ach(_reg_PI_TREF_F1, 0x0000); |
| 2346 | ddr_setval_ach(_reg_PI_TREF_F2, 0x0000); |
| 2347 | |
| 2348 | if (Prr_Product == PRR_PRODUCT_M3) { |
| 2349 | ddr_setval_ach(_reg_PI_WDQLVL_EN, 0x02); |
| 2350 | } else { |
| 2351 | ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x02); |
| 2352 | } |
| 2353 | ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01); |
| 2354 | |
| 2355 | /* DFI_PHYMSTR_ACK , WTmode setting */ |
| 2356 | mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011); /* DFI_PHYMSTR_ACK: WTmode =b'01 */ |
| 2357 | } |
| 2358 | #endif /* RCAR_REWT_TRAINING */ |
| 2359 | /* periodic dram zqcal and phy ctrl update enable */ |
| 2360 | mmio_write_32(DBSC_DBCALCNF, 0x01000010); |
| 2361 | if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) |
| 2362 | || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20))) { |
| 2363 | /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ |
| 2364 | } else { |
| 2365 | #if RCAR_DRAM_SPLIT == 2 |
| 2366 | if ((Prr_Product == PRR_PRODUCT_H3) |
| 2367 | && (Boardcnf->phyvalid == 0x05)) |
| 2368 | mmio_write_32(DBSC_DBDFICUPDCNF, 0x2a240001); |
| 2369 | else |
| 2370 | mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001); |
| 2371 | #else /* RCAR_DRAM_SPLIT == 2 */ |
| 2372 | mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001); |
| 2373 | #endif /* RCAR_DRAM_SPLIT == 2 */ |
| 2374 | } |
| 2375 | |
| 2376 | #ifdef DDR_BACKUPMODE |
| 2377 | if (ddrBackup == DRAM_BOOT_STATUS_WARM) { |
| 2378 | #ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0,1 only) */ |
| 2379 | PutStr(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1); |
| 2380 | send_dbcmd(0x08040001); |
| 2381 | wait_dbcmd(); |
| 2382 | send_dbcmd(0x0A040001); |
| 2383 | wait_dbcmd(); |
| 2384 | send_dbcmd(0x04040010); |
| 2385 | wait_dbcmd(); |
| 2386 | |
| 2387 | if (Prr_Product == PRR_PRODUCT_H3) { |
| 2388 | send_dbcmd(0x08140001); |
| 2389 | wait_dbcmd(); |
| 2390 | send_dbcmd(0x0A140001); |
| 2391 | wait_dbcmd(); |
| 2392 | send_dbcmd(0x04140010); |
| 2393 | wait_dbcmd(); |
| 2394 | } |
| 2395 | #else /* DDR_BACKUPMODE_HALF //for All channels */ |
| 2396 | send_dbcmd(0x08840001); |
| 2397 | wait_dbcmd(); |
| 2398 | send_dbcmd(0x0A840001); |
| 2399 | wait_dbcmd(); |
| 2400 | |
| 2401 | send_dbcmd(0x04840010); |
| 2402 | wait_dbcmd(); |
| 2403 | #endif /* DDR_BACKUPMODE_HALF */ |
| 2404 | } |
| 2405 | #endif /* DDR_BACKUPMODE */ |
| 2406 | |
| 2407 | mmio_write_32(DBSC_DBRFEN, 0x00000001); |
| 2408 | /* dram access enable */ |
| 2409 | mmio_write_32(DBSC_DBACEN, 0x00000001); |
| 2410 | |
| 2411 | MSG_LF("dbsc_regset_post(done)"); |
| 2412 | |
| 2413 | } |
| 2414 | |
| 2415 | /******************************************************************************* |
| 2416 | * DFI_INIT_START |
| 2417 | ******************************************************************************/ |
| 2418 | static uint32_t dfi_init_start(void) |
| 2419 | { |
| 2420 | uint32_t ch; |
| 2421 | uint32_t phytrainingok; |
| 2422 | uint32_t retry; |
| 2423 | uint32_t dataL; |
| 2424 | const uint32_t RETRY_MAX = 0x10000; |
| 2425 | |
| 2426 | /*********************************************************************** |
| 2427 | set IE=1 when init_start_disable==0 |
| 2428 | ***********************************************************************/ |
| 2429 | if (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_CAL_MODE_0) & |
| 2430 | 0x01) { |
| 2431 | ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00); |
| 2432 | } else { |
| 2433 | ddr_setval_ach_as(_reg_PHY_IE_MODE, |
| 2434 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, |
| 2435 | _reg_PHY_IE_MODE)); |
| 2436 | } |
| 2437 | |
| 2438 | if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { |
| 2439 | |
| 2440 | /*********************************************************************** |
| 2441 | PLL3 Disable |
| 2442 | ***********************************************************************/ |
| 2443 | /* protect register interface */ |
| 2444 | ddrphy_regif_idle(); |
| 2445 | |
| 2446 | pll3_control(0); |
| 2447 | |
| 2448 | /*********************************************************************** |
| 2449 | init start |
| 2450 | ***********************************************************************/ |
| 2451 | /* dbdficnt0: |
| 2452 | * dfi_dram_clk_disable=1 |
| 2453 | * dfi_frequency = 0 |
| 2454 | * freq_ratio = 01 (2:1) |
| 2455 | * init_start =0 |
| 2456 | */ |
| 2457 | foreach_vch(ch) |
| 2458 | mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10); |
| 2459 | dsb_sev(); |
| 2460 | |
| 2461 | /* dbdficnt0: |
| 2462 | * dfi_dram_clk_disable=1 |
| 2463 | * dfi_frequency = 0 |
| 2464 | * freq_ratio = 01 (2:1) |
| 2465 | * init_start =1 |
| 2466 | */ |
| 2467 | foreach_vch(ch) |
| 2468 | mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11); |
| 2469 | dsb_sev(); |
| 2470 | |
| 2471 | } else { |
| 2472 | ddr_setval_ach_as(_reg_PHY_DLL_RST_EN, 0x02); |
| 2473 | dsb_sev(); |
| 2474 | ddrphy_regif_idle(); |
| 2475 | } |
| 2476 | |
| 2477 | /* dll_rst negate */ |
| 2478 | foreach_vch(ch) |
| 2479 | mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01); |
| 2480 | dsb_sev(); |
| 2481 | |
| 2482 | /*********************************************************************** |
| 2483 | wait init_complete |
| 2484 | ***********************************************************************/ |
| 2485 | phytrainingok = 0; |
| 2486 | retry = 0; |
| 2487 | while (retry++ < RETRY_MAX) { |
| 2488 | foreach_vch(ch) { |
| 2489 | dataL = mmio_read_32(DBSC_INITCOMP(ch)); |
| 2490 | if (dataL & 0x00000001) |
| 2491 | phytrainingok |= (1U << ch); |
| 2492 | } |
| 2493 | dsb_sev(); |
| 2494 | if (phytrainingok == ddr_phyvalid) |
| 2495 | break; |
| 2496 | if (retry % 256 == 0) |
| 2497 | ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01); |
| 2498 | } |
| 2499 | |
| 2500 | /*********************************************************************** |
| 2501 | all ch ok? |
| 2502 | ***********************************************************************/ |
| 2503 | if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) { |
| 2504 | return (0xff); |
| 2505 | } |
| 2506 | /* dbdficnt0: |
| 2507 | * dfi_dram_clk_disable=0 |
| 2508 | * dfi_frequency = 0 |
| 2509 | * freq_ratio = 01 (2:1) |
| 2510 | * init_start =0 |
| 2511 | */ |
| 2512 | foreach_vch(ch) |
| 2513 | mmio_write_32(DBSC_DBDFICNT(ch), 0x00000010); |
| 2514 | dsb_sev(); |
| 2515 | |
| 2516 | return 0; |
| 2517 | } |
| 2518 | |
| 2519 | /******************************************************************************* |
| 2520 | * drivablity setting : CMOS MODE ON/OFF |
| 2521 | ******************************************************************************/ |
| 2522 | static void change_lpddr4_en(uint32_t mode) |
| 2523 | { |
| 2524 | uint32_t ch; |
| 2525 | uint32_t i; |
| 2526 | uint32_t dataL; |
| 2527 | const uint32_t _reg_PHY_PAD_DRIVE_X[3] = { |
| 2528 | _reg_PHY_PAD_ADDR_DRIVE, |
| 2529 | _reg_PHY_PAD_CLK_DRIVE, |
| 2530 | _reg_PHY_PAD_CS_DRIVE |
| 2531 | }; |
| 2532 | |
| 2533 | for (i = 0; i < 3; i++) { |
| 2534 | foreach_vch(ch) { |
| 2535 | dataL = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]); |
| 2536 | if (mode) { |
| 2537 | dataL |= (1U << 14); |
| 2538 | } else { |
| 2539 | dataL &= ~(1U << 14); |
| 2540 | } |
| 2541 | ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], dataL); |
| 2542 | } |
| 2543 | } |
| 2544 | } |
| 2545 | |
| 2546 | /******************************************************************************* |
| 2547 | * drivablity setting |
| 2548 | ******************************************************************************/ |
| 2549 | static uint32_t set_term_code(void) |
| 2550 | { |
| 2551 | int32_t i; |
| 2552 | uint32_t ch, index; |
| 2553 | uint32_t dataL; |
| 2554 | uint32_t chip_id[2]; |
| 2555 | uint32_t term_code; |
| 2556 | uint32_t override; |
| 2557 | term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, |
| 2558 | _reg_PHY_PAD_DATA_TERM); |
| 2559 | override = 0; |
| 2560 | for (i = 0; i < 2; i++) |
| 2561 | chip_id[i] = mmio_read_32(LIFEC_CHIPID(i)); |
| 2562 | |
| 2563 | index = 0; |
| 2564 | while (1) { |
| 2565 | if (TermcodeBySample[index][0] == 0xffffffff) { |
| 2566 | break; |
| 2567 | } |
| 2568 | if ((TermcodeBySample[index][0] == chip_id[0]) |
| 2569 | && (TermcodeBySample[index][1] == chip_id[1])) { |
| 2570 | term_code = TermcodeBySample[index][2]; |
| 2571 | override = 1; |
| 2572 | break; |
| 2573 | } |
| 2574 | index++; |
| 2575 | } |
| 2576 | |
| 2577 | if (override) { |
| 2578 | for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) { |
| 2579 | dataL = |
| 2580 | ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, |
| 2581 | _reg_PHY_PAD_TERM_X[index]); |
| 2582 | dataL = (dataL & ~0x0001ffff) | term_code; |
| 2583 | ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], dataL); |
| 2584 | } |
| 2585 | } else if ((Prr_Product == PRR_PRODUCT_M3) |
| 2586 | && (Prr_Cut == PRR_PRODUCT_10)) { |
| 2587 | /* non */ |
| 2588 | } else { |
| 2589 | ddr_setval_ach_as(_reg_PHY_IE_MODE, |
| 2590 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, |
| 2591 | _reg_PHY_IE_MODE)); |
| 2592 | ddr_setval_ach(_reg_PHY_PAD_TERM_X[0], |
| 2593 | (ddrtbl_getval |
| 2594 | (_cnf_DDR_PHY_ADR_G_REGSET, |
| 2595 | _reg_PHY_PAD_TERM_X[0]) & 0xFFFE0000)); |
| 2596 | ddr_setval_ach(_reg_PHY_CAL_CLEAR_0, 0x01); |
| 2597 | ddr_setval_ach(_reg_PHY_CAL_START_0, 0x01); |
| 2598 | foreach_vch(ch) { |
| 2599 | do { |
| 2600 | dataL = |
| 2601 | ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); |
| 2602 | } while (!(dataL & 0x00800000)); |
| 2603 | } |
| 2604 | if ((Prr_Product == PRR_PRODUCT_H3) |
| 2605 | && (Prr_Cut <= PRR_PRODUCT_11)) { |
| 2606 | foreach_vch(ch) { |
| 2607 | uint32_t pvtr; |
| 2608 | uint32_t pvtp; |
| 2609 | uint32_t pvtn; |
| 2610 | dataL = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]); |
| 2611 | pvtr = (dataL >> 12) & 0x1f; |
| 2612 | pvtr += 8; |
| 2613 | if (pvtr > 0x1f) |
| 2614 | pvtr = 0x1f; |
| 2615 | dataL = |
| 2616 | ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); |
| 2617 | pvtn = (dataL >> 6) & 0x03f; |
| 2618 | pvtp = (dataL >> 0) & 0x03f; |
| 2619 | |
| 2620 | for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; |
| 2621 | index++) { |
| 2622 | dataL = |
| 2623 | ddrtbl_getval |
| 2624 | (_cnf_DDR_PHY_ADR_G_REGSET, |
| 2625 | _reg_PHY_PAD_TERM_X[index]); |
| 2626 | dataL = (dataL & ~0x0001ffff) |
| 2627 | | (pvtr << 12) |
| 2628 | | (pvtn << 6) |
| 2629 | | (pvtp); |
| 2630 | ddr_setval(ch, |
| 2631 | _reg_PHY_PAD_TERM_X[index], |
| 2632 | dataL); |
| 2633 | } |
| 2634 | } |
| 2635 | } else { /* M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */ |
| 2636 | foreach_vch(ch) { |
| 2637 | for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; |
| 2638 | index++) { |
| 2639 | dataL = |
| 2640 | ddr_getval(ch, |
| 2641 | _reg_PHY_PAD_TERM_X |
| 2642 | [index]); |
| 2643 | ddr_setval(ch, |
| 2644 | _reg_PHY_PAD_TERM_X[index], |
| 2645 | (dataL & 0xFFFE0FFF) | |
| 2646 | 0x00015000); |
| 2647 | } |
| 2648 | } |
| 2649 | } |
| 2650 | } |
| 2651 | if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { |
| 2652 | /* non */ |
| 2653 | } else { |
| 2654 | ddr_padcal_tcompensate_getinit(override); |
| 2655 | } |
| 2656 | return 0; |
| 2657 | } |
| 2658 | |
| 2659 | /******************************************************************************* |
| 2660 | * DDR mode register setting |
| 2661 | ******************************************************************************/ |
| 2662 | static void ddr_register_set(uint32_t ch) |
| 2663 | { |
| 2664 | int32_t fspwp; |
| 2665 | uint32_t chind; |
| 2666 | uint32_t tmp; |
| 2667 | |
| 2668 | chind = ch << 20; |
| 2669 | for (fspwp = 1; fspwp >= 0; fspwp--) { |
| 2670 | /*MR13,fspwp */ |
| 2671 | send_dbcmd(0x0e040d08 | chind | (fspwp << 6)); |
| 2672 | |
| 2673 | tmp = |
| 2674 | ddrtbl_getval(_cnf_DDR_PI_REGSET, |
| 2675 | _reg_PI_MR1_DATA_Fx_CSx[fspwp][0]); |
| 2676 | send_dbcmd(0x0e040100 | chind | tmp); |
| 2677 | |
| 2678 | tmp = |
| 2679 | ddrtbl_getval(_cnf_DDR_PI_REGSET, |
| 2680 | _reg_PI_MR2_DATA_Fx_CSx[fspwp][0]); |
| 2681 | send_dbcmd(0x0e040200 | chind | tmp); |
| 2682 | |
| 2683 | tmp = |
| 2684 | ddrtbl_getval(_cnf_DDR_PI_REGSET, |
| 2685 | _reg_PI_MR3_DATA_Fx_CSx[fspwp][0]); |
| 2686 | send_dbcmd(0x0e040300 | chind | tmp); |
| 2687 | |
| 2688 | tmp = |
| 2689 | ddrtbl_getval(_cnf_DDR_PI_REGSET, |
| 2690 | _reg_PI_MR11_DATA_Fx_CSx[fspwp][0]); |
| 2691 | send_dbcmd(0x0e040b00 | chind | tmp); |
| 2692 | |
| 2693 | tmp = |
| 2694 | ddrtbl_getval(_cnf_DDR_PI_REGSET, |
| 2695 | _reg_PI_MR12_DATA_Fx_CSx[fspwp][0]); |
| 2696 | send_dbcmd(0x0e040c00 | chind | tmp); |
| 2697 | |
| 2698 | tmp = |
| 2699 | ddrtbl_getval(_cnf_DDR_PI_REGSET, |
| 2700 | _reg_PI_MR14_DATA_Fx_CSx[fspwp][0]); |
| 2701 | send_dbcmd(0x0e040e00 | chind | tmp); |
| 2702 | /* MR22 */ |
| 2703 | send_dbcmd(0x0e041600 | chind | 0x16); |
| 2704 | } |
| 2705 | } |
| 2706 | |
| 2707 | /******************************************************************************* |
| 2708 | * Training handshake functions |
| 2709 | ******************************************************************************/ |
| 2710 | static inline uint32_t wait_freqchgreq(uint32_t assert) |
| 2711 | { |
| 2712 | uint32_t dataL; |
| 2713 | uint32_t count; |
| 2714 | uint32_t ch; |
| 2715 | count = 100000; |
| 2716 | |
| 2717 | /* H3 Ver.1.x cannot see frqchg_req */ |
| 2718 | if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { |
| 2719 | return 0; |
| 2720 | } |
| 2721 | |
| 2722 | if (assert) { |
| 2723 | do { |
| 2724 | dataL = 1; |
| 2725 | foreach_vch(ch) { |
| 2726 | dataL &= mmio_read_32(DBSC_DBPDSTAT(ch)); |
| 2727 | } |
| 2728 | count = count - 1; |
| 2729 | } while (((dataL & 0x01) != 0x01) & (count != 0)); |
| 2730 | } else { |
| 2731 | do { |
| 2732 | dataL = 0; |
| 2733 | foreach_vch(ch) { |
| 2734 | dataL |= mmio_read_32(DBSC_DBPDSTAT(ch)); |
| 2735 | } |
| 2736 | count = count - 1; |
| 2737 | } while (((dataL & 0x01) != 0x00) & (count != 0)); |
| 2738 | } |
| 2739 | |
| 2740 | return (count == 0); |
| 2741 | } |
| 2742 | |
| 2743 | static inline void set_freqchgack(uint32_t assert) |
| 2744 | { |
| 2745 | uint32_t ch; |
| 2746 | uint32_t dataL; |
| 2747 | if (assert) |
| 2748 | dataL = 0x0CF20000; |
| 2749 | else |
| 2750 | dataL = 0x00000000; |
| 2751 | |
| 2752 | foreach_vch(ch) |
| 2753 | mmio_write_32(DBSC_DBPDCNT2(ch), dataL); |
| 2754 | } |
| 2755 | |
| 2756 | static inline void set_dfifrequency(uint32_t freq) |
| 2757 | { |
| 2758 | uint32_t ch; |
| 2759 | if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { |
| 2760 | foreach_vch(ch) |
| 2761 | mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq); |
| 2762 | } else { |
| 2763 | foreach_vch(ch) { |
| 2764 | mmio_clrsetbits_32(DBSC_DBDFICNT(ch), 0x1fU << 24, |
| 2765 | (freq << 24)); |
| 2766 | } |
| 2767 | } |
| 2768 | dsb_sev(); |
| 2769 | } |
| 2770 | |
| 2771 | static uint32_t pll3_freq(uint32_t on) |
| 2772 | { |
| 2773 | uint32_t timeout; |
| 2774 | |
| 2775 | timeout = wait_freqchgreq(1); |
| 2776 | |
| 2777 | if (timeout) { |
| 2778 | return (1); |
| 2779 | } |
| 2780 | |
| 2781 | pll3_control(on); |
| 2782 | set_dfifrequency(on); |
| 2783 | |
| 2784 | set_freqchgack(1); |
| 2785 | timeout = wait_freqchgreq(0); |
| 2786 | set_freqchgack(0); |
| 2787 | |
| 2788 | if (timeout) { |
| 2789 | FATAL_MSG("Time out[2]"); |
| 2790 | return (1); |
| 2791 | } |
| 2792 | return (0); |
| 2793 | } |
| 2794 | |
| 2795 | /******************************************************************************* |
| 2796 | * update dly |
| 2797 | ******************************************************************************/ |
| 2798 | static void update_dly(void) |
| 2799 | { |
| 2800 | ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01); |
| 2801 | ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01); |
| 2802 | } |
| 2803 | |
| 2804 | /******************************************************************************* |
| 2805 | * training by pi |
| 2806 | ******************************************************************************/ |
| 2807 | static uint32_t pi_training_go(void) |
| 2808 | { |
| 2809 | uint32_t flag; |
| 2810 | uint32_t dataL; |
| 2811 | uint32_t retry; |
| 2812 | const uint32_t RETRY_MAX = 4096 * 16; |
| 2813 | uint32_t ch; |
| 2814 | |
| 2815 | uint32_t mst_ch; |
| 2816 | uint32_t cur_frq; |
| 2817 | uint32_t complete; |
| 2818 | uint32_t frqchg_req; |
| 2819 | |
| 2820 | /* ********************************************************************* */ |
| 2821 | |
| 2822 | /*********************************************************************** |
| 2823 | pi_start |
| 2824 | ***********************************************************************/ |
| 2825 | ddr_setval_ach(_reg_PI_START, 0x01); |
| 2826 | foreach_vch(ch) |
| 2827 | ddr_getval(ch, _reg_PI_INT_STATUS); |
| 2828 | |
| 2829 | /* set dfi_phymstr_ack = 1 */ |
| 2830 | mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001); |
| 2831 | dsb_sev(); |
| 2832 | |
| 2833 | /*********************************************************************** |
| 2834 | wait pi_int_status[0] |
| 2835 | ***********************************************************************/ |
| 2836 | mst_ch = 0; |
| 2837 | flag = 0; |
| 2838 | complete = 0; |
| 2839 | cur_frq = 0; |
| 2840 | retry = RETRY_MAX; |
| 2841 | do { |
| 2842 | frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01; |
| 2843 | |
| 2844 | /* H3 Ver.1.x cannot see frqchg_req */ |
| 2845 | if ((Prr_Product == PRR_PRODUCT_H3) |
| 2846 | && (Prr_Cut <= PRR_PRODUCT_11)) { |
| 2847 | if ((retry % 4096) == 1) { |
| 2848 | frqchg_req = 1; |
| 2849 | } else { |
| 2850 | frqchg_req = 0; |
| 2851 | } |
| 2852 | } |
| 2853 | |
| 2854 | if (frqchg_req) { |
| 2855 | if (cur_frq) { |
| 2856 | /* Low frequency */ |
| 2857 | flag = pll3_freq(0); |
| 2858 | cur_frq = 0; |
| 2859 | } else { |
| 2860 | /* High frequency */ |
| 2861 | flag = pll3_freq(1); |
| 2862 | cur_frq = 1; |
| 2863 | } |
| 2864 | if (flag) |
| 2865 | break; |
| 2866 | } else { |
| 2867 | if (cur_frq) { |
| 2868 | foreach_vch(ch) { |
| 2869 | if (complete & (1U << ch)) |
| 2870 | continue; |
| 2871 | dataL = |
| 2872 | ddr_getval(ch, _reg_PI_INT_STATUS); |
| 2873 | if (dataL & 0x01) { |
| 2874 | complete |= (1U << ch); |
| 2875 | } |
| 2876 | } |
| 2877 | if (complete == ddr_phyvalid) |
| 2878 | break; |
| 2879 | } |
| 2880 | } |
| 2881 | } while (--retry); |
| 2882 | foreach_vch(ch) { |
| 2883 | /* dummy read */ |
| 2884 | dataL = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0); |
| 2885 | dataL = ddr_getval(ch, _reg_PI_INT_STATUS); |
| 2886 | ddr_setval(ch, _reg_PI_INT_ACK, dataL); |
| 2887 | } |
| 2888 | if (ddrphy_regif_chk()) { |
| 2889 | return (0xfd); |
| 2890 | } |
| 2891 | return complete; |
| 2892 | } |
| 2893 | |
| 2894 | /******************************************************************************* |
| 2895 | * Initialize ddr |
| 2896 | ******************************************************************************/ |
| 2897 | static uint32_t init_ddr(void) |
| 2898 | { |
| 2899 | int32_t i; |
| 2900 | uint32_t dataL; |
| 2901 | uint32_t phytrainingok; |
| 2902 | uint32_t ch; |
| 2903 | uint32_t err; |
| 2904 | |
| 2905 | MSG_LF("init_ddr:0\n"); |
| 2906 | |
| 2907 | #ifdef DDR_BACKUPMODE |
| 2908 | rcar_dram_get_boot_status(&ddrBackup); |
| 2909 | #endif |
| 2910 | |
| 2911 | /*********************************************************************** |
| 2912 | unlock phy |
| 2913 | ***********************************************************************/ |
| 2914 | /* Unlock DDRPHY register(AGAIN) */ |
| 2915 | foreach_vch(ch) |
| 2916 | mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55A); |
| 2917 | dsb_sev(); |
| 2918 | |
| 2919 | if ((((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) |
| 2920 | || (Prr_Product == PRR_PRODUCT_M3N) |
| 2921 | || (Prr_Product == PRR_PRODUCT_V3H)) && (Boardcnf->dbi_en)) |
| 2922 | reg_ddrphy_write_a(0x00001010, 0x01000001); |
| 2923 | else |
| 2924 | reg_ddrphy_write_a(0x00001010, 0x00000001); |
| 2925 | /*********************************************************************** |
| 2926 | dbsc register pre-setting |
| 2927 | ***********************************************************************/ |
| 2928 | dbsc_regset_pre(); |
| 2929 | |
| 2930 | /*********************************************************************** |
| 2931 | load ddrphy registers |
| 2932 | ***********************************************************************/ |
| 2933 | |
| 2934 | ddrtbl_load(); |
| 2935 | |
| 2936 | /*********************************************************************** |
| 2937 | configure ddrphy registers |
| 2938 | ***********************************************************************/ |
| 2939 | ddr_config(); |
| 2940 | |
| 2941 | /*********************************************************************** |
| 2942 | dfi_reset assert |
| 2943 | ***********************************************************************/ |
| 2944 | foreach_vch(ch) |
| 2945 | mmio_write_32(DBSC_DBPDCNT0(ch), 0x01); |
| 2946 | dsb_sev(); |
| 2947 | |
| 2948 | /*********************************************************************** |
| 2949 | dbsc register set |
| 2950 | ***********************************************************************/ |
| 2951 | dbsc_regset(); |
| 2952 | MSG_LF("init_ddr:1\n"); |
| 2953 | |
| 2954 | /*********************************************************************** |
| 2955 | dfi_reset negate |
| 2956 | ***********************************************************************/ |
| 2957 | foreach_vch(ch) |
| 2958 | mmio_write_32(DBSC_DBPDCNT0(ch), 0x00); |
| 2959 | dsb_sev(); |
| 2960 | |
| 2961 | /*********************************************************************** |
| 2962 | dfi_init_start (start ddrphy) |
| 2963 | ***********************************************************************/ |
| 2964 | err = dfi_init_start(); |
| 2965 | if (err) { |
| 2966 | return INITDRAM_ERR_I; |
| 2967 | } |
| 2968 | MSG_LF("init_ddr:2\n"); |
| 2969 | |
| 2970 | /*********************************************************************** |
| 2971 | ddr backupmode end |
| 2972 | ***********************************************************************/ |
| 2973 | #ifdef DDR_BACKUPMODE |
| 2974 | if (ddrBackup) { |
| 2975 | NOTICE("[WARM_BOOT]"); |
| 2976 | } else { |
| 2977 | NOTICE("[COLD_BOOT]"); |
| 2978 | } |
| 2979 | err = rcar_dram_update_boot_status(ddrBackup); |
| 2980 | if (err) { |
| 2981 | NOTICE("[BOOT_STATUS_UPDATE_ERROR]"); |
| 2982 | return INITDRAM_ERR_I; |
| 2983 | } |
| 2984 | #endif |
| 2985 | MSG_LF("init_ddr:3\n"); |
| 2986 | |
| 2987 | /*********************************************************************** |
| 2988 | override term code after dfi_init_complete |
| 2989 | ***********************************************************************/ |
| 2990 | err = set_term_code(); |
| 2991 | if (err) { |
| 2992 | return INITDRAM_ERR_I; |
| 2993 | } |
| 2994 | MSG_LF("init_ddr:4\n"); |
| 2995 | |
| 2996 | /*********************************************************************** |
| 2997 | rx offset calibration |
| 2998 | ***********************************************************************/ |
| 2999 | if ((Prr_Cut > PRR_PRODUCT_11) || (Prr_Product == PRR_PRODUCT_M3N) |
| 3000 | || (Prr_Product == PRR_PRODUCT_V3H)) { |
| 3001 | err = rx_offset_cal_hw(); |
| 3002 | } else { |
| 3003 | err = rx_offset_cal(); |
| 3004 | } |
| 3005 | if (err) |
| 3006 | return (INITDRAM_ERR_O); |
| 3007 | MSG_LF("init_ddr:5\n"); |
| 3008 | |
| 3009 | /*********************************************************************** |
| 3010 | set ie_mode=1 |
| 3011 | ***********************************************************************/ |
| 3012 | ddr_setval_ach_as(_reg_PHY_IE_MODE, |
| 3013 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, |
| 3014 | _reg_PHY_IE_MODE)); |
| 3015 | |
| 3016 | /*********************************************************************** |
| 3017 | check register i/f is alive |
| 3018 | ***********************************************************************/ |
| 3019 | err = ddrphy_regif_chk(); |
| 3020 | if (err) { |
| 3021 | return (INITDRAM_ERR_O); |
| 3022 | } |
| 3023 | MSG_LF("init_ddr:6\n"); |
| 3024 | |
| 3025 | /*********************************************************************** |
| 3026 | phy initialize end |
| 3027 | ***********************************************************************/ |
| 3028 | |
| 3029 | /*********************************************************************** |
| 3030 | setup DDR mode registers |
| 3031 | ***********************************************************************/ |
| 3032 | /* CMOS MODE */ |
| 3033 | change_lpddr4_en(0); |
| 3034 | |
| 3035 | ch = 0x08; |
| 3036 | |
| 3037 | /* PDE */ |
| 3038 | send_dbcmd(0x08040000 | (0x00100000 * ch)); |
| 3039 | |
| 3040 | /* PDX */ |
| 3041 | send_dbcmd(0x08040001 | (0x00100000 * ch)); |
| 3042 | |
| 3043 | /* MR22 (ODTCS & RQZ */ |
| 3044 | send_dbcmd(0x0e041600 | (0x00100000 * ch) | 0x16); |
| 3045 | |
| 3046 | /* ZQCAL start */ |
| 3047 | send_dbcmd(0x0d04004F | (0x00100000 * ch)); |
| 3048 | rcar_micro_delay(100); |
| 3049 | |
| 3050 | /* ZQLAT */ |
| 3051 | send_dbcmd(0x0d040051 | (0x00100000 * ch)); |
| 3052 | |
| 3053 | /*********************************************************************** |
| 3054 | Thermal sensor setting |
| 3055 | ***********************************************************************/ |
| 3056 | /* THCTR Bit6: PONM=0 , Bit0: THSST=1 */ |
| 3057 | dataL = |
| 3058 | ((*((volatile uint32_t *)THS1_THCTR)) & 0xFFFFFFBF) | 0x00000001; |
| 3059 | *((volatile uint32_t *)THS1_THCTR) = dataL; |
| 3060 | |
| 3061 | /*********************************************************************** |
| 3062 | setup DDR mode registers |
| 3063 | ***********************************************************************/ |
| 3064 | foreach_vch(ch) { |
| 3065 | ddr_register_set(ch); |
| 3066 | } |
| 3067 | /* LPDDR4 MODE */ |
| 3068 | change_lpddr4_en(1); |
| 3069 | |
| 3070 | MSG_LF("init_ddr:7\n"); |
| 3071 | |
| 3072 | /*********************************************************************** |
| 3073 | mask CS_MAP if RANKx is not found |
| 3074 | ***********************************************************************/ |
| 3075 | foreach_vch(ch) { |
| 3076 | dataL = ddr_getval(ch, _reg_PI_CS_MAP); |
| 3077 | if (!(ch_have_this_cs[0] & (1U << ch))) |
| 3078 | dataL = dataL & 0x0a; |
| 3079 | if (!(ch_have_this_cs[1] & (1U << ch))) |
| 3080 | dataL = dataL & 0x05; |
| 3081 | ddr_setval(ch, _reg_PI_CS_MAP, dataL); |
| 3082 | } |
| 3083 | |
| 3084 | /*********************************************************************** |
| 3085 | exec pi_training |
| 3086 | ***********************************************************************/ |
| 3087 | ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00); |
| 3088 | ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01); |
| 3089 | |
| 3090 | phytrainingok = pi_training_go(); |
| 3091 | |
| 3092 | if (ddr_phyvalid != (phytrainingok & ddr_phyvalid)) { |
| 3093 | return (INITDRAM_ERR_T | phytrainingok); |
| 3094 | } |
| 3095 | |
| 3096 | MSG_LF("init_ddr:8\n"); |
| 3097 | |
| 3098 | /*********************************************************************** |
| 3099 | CACS DLY ADJUST |
| 3100 | ***********************************************************************/ |
| 3101 | dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj); |
| 3102 | foreach_vch(ch) { |
| 3103 | int16_t adj; |
| 3104 | for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { |
| 3105 | adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]); |
| 3106 | ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], |
| 3107 | dataL + adj); |
| 3108 | } |
| 3109 | } |
| 3110 | update_dly(); |
| 3111 | MSG_LF("init_ddr:9\n"); |
| 3112 | |
| 3113 | /*********************************************************************** |
| 3114 | H3 fix rd latency to avoid bug in elasitic buffe |
| 3115 | ***********************************************************************/ |
| 3116 | if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { |
| 3117 | adjust_rddqs_latency(); |
| 3118 | } |
| 3119 | |
| 3120 | /*********************************************************************** |
| 3121 | Adjust Write path latency |
| 3122 | ***********************************************************************/ |
| 3123 | if (ddrtbl_getval |
| 3124 | (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) |
| 3125 | adjust_wpath_latency(); |
| 3126 | |
| 3127 | /*********************************************************************** |
| 3128 | RDQLVL Training |
| 3129 | ***********************************************************************/ |
| 3130 | if ((Prr_Product == PRR_PRODUCT_H3) || (Prr_Product == PRR_PRODUCT_M3)) { |
| 3131 | ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01); |
| 3132 | } else { |
| 3133 | ddr_setval_ach_as(_reg_PHY_IE_MODE, |
| 3134 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, |
| 3135 | _reg_PHY_IE_MODE)); |
| 3136 | } |
| 3137 | |
| 3138 | err = rdqdm_man(); |
| 3139 | if (err) { |
| 3140 | return (INITDRAM_ERR_T); |
| 3141 | } |
| 3142 | update_dly(); |
| 3143 | MSG_LF("init_ddr:10\n"); |
| 3144 | |
| 3145 | /*********************************************************************** |
| 3146 | WDQLVL Training |
| 3147 | ***********************************************************************/ |
| 3148 | err = wdqdm_man(); |
| 3149 | if (err) { |
| 3150 | return (INITDRAM_ERR_T); |
| 3151 | } |
| 3152 | update_dly(); |
| 3153 | MSG_LF("init_ddr:11\n"); |
| 3154 | |
| 3155 | /*********************************************************************** |
| 3156 | training complete, setup dbsc |
| 3157 | ***********************************************************************/ |
| 3158 | if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) |
| 3159 | || (Prr_Product == PRR_PRODUCT_M3N) |
| 3160 | || (Prr_Product == PRR_PRODUCT_V3H)) { |
| 3161 | ddr_setval_ach_as(_reg_PHY_DFI40_POLARITY, 0x00); |
| 3162 | ddr_setval_ach(_reg_PI_DFI40_POLARITY, 0x00); |
| 3163 | } |
| 3164 | |
| 3165 | dbsc_regset_post(); |
| 3166 | MSG_LF("init_ddr:12\n"); |
| 3167 | |
| 3168 | return phytrainingok; |
| 3169 | } |
| 3170 | |
| 3171 | /******************************************************************************* |
| 3172 | * SW LEVELING COMMON |
| 3173 | ******************************************************************************/ |
| 3174 | static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick) |
| 3175 | { |
| 3176 | uint32_t ch; |
| 3177 | uint32_t dataL; |
| 3178 | uint32_t retry; |
| 3179 | uint32_t waiting; |
| 3180 | uint32_t err; |
| 3181 | |
| 3182 | const uint32_t RETRY_MAX = 0x1000; |
| 3183 | |
| 3184 | err = 0; |
| 3185 | /* set EXIT -> OP_DONE is cleared */ |
| 3186 | ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01); |
| 3187 | |
| 3188 | /* kick */ |
| 3189 | foreach_vch(ch) { |
| 3190 | if (ch_have_this_cs[ddr_csn % 2] & (1U << ch)) { |
| 3191 | ddr_setval(ch, reg_cs, ddr_csn); |
| 3192 | ddr_setval(ch, reg_kick, 0x01); |
| 3193 | } |
| 3194 | } |
| 3195 | foreach_vch(ch) { |
| 3196 | /*PREPARE ADDR REGISTER (for SWLVL_OP_DONE) */ |
| 3197 | ddr_getval(ch, _reg_PI_SWLVL_OP_DONE); |
| 3198 | } |
| 3199 | waiting = ch_have_this_cs[ddr_csn % 2]; |
| 3200 | dsb_sev(); |
| 3201 | retry = RETRY_MAX; |
| 3202 | do { |
| 3203 | foreach_vch(ch) { |
| 3204 | if (!(waiting & (1U << ch))) |
| 3205 | continue; |
| 3206 | dataL = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE); |
| 3207 | if (dataL & 0x01) |
| 3208 | waiting &= ~(1U << ch); |
| 3209 | } |
| 3210 | retry--; |
| 3211 | } while (waiting && (retry > 0)); |
| 3212 | if (retry == 0) { |
| 3213 | err = 1; |
| 3214 | } |
| 3215 | |
| 3216 | dsb_sev(); |
| 3217 | /* set EXIT -> OP_DONE is cleared */ |
| 3218 | ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01); |
| 3219 | dsb_sev(); |
| 3220 | |
| 3221 | return err; |
| 3222 | } |
| 3223 | |
| 3224 | /******************************************************************************* |
| 3225 | * WDQ TRAINING |
| 3226 | ******************************************************************************/ |
| 3227 | static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn) |
| 3228 | { |
| 3229 | int32_t i, k; |
| 3230 | uint32_t cs, slice; |
| 3231 | uint32_t dataL; |
| 3232 | |
| 3233 | /*********************************************************************** |
| 3234 | clr of training results buffer |
| 3235 | ***********************************************************************/ |
| 3236 | cs = ddr_csn % 2; |
| 3237 | dataL = Boardcnf->dqdm_dly_w; |
| 3238 | for (slice = 0; slice < SLICE_CNT; slice++) { |
| 3239 | k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; |
| 3240 | if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) |
| 3241 | continue; |
| 3242 | |
| 3243 | for (i = 0; i <= 8; i++) { |
| 3244 | if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) |
| 3245 | wdqdm_dly[ch][cs][slice][i] = |
| 3246 | wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i]; |
| 3247 | else |
| 3248 | wdqdm_dly[ch][cs][slice][i] = dataL; |
| 3249 | wdqdm_le[ch][cs][slice][i] = 0; |
| 3250 | wdqdm_te[ch][cs][slice][i] = 0; |
| 3251 | } |
| 3252 | wdqdm_st[ch][cs][slice] = 0; |
| 3253 | wdqdm_win[ch][cs][slice] = 0; |
| 3254 | } |
| 3255 | } |
| 3256 | |
| 3257 | static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn) |
| 3258 | { |
| 3259 | int32_t i, k; |
| 3260 | uint32_t cs, slice; |
| 3261 | uint32_t dataL; |
| 3262 | uint32_t err; |
| 3263 | const uint32_t _par_WDQLVL_RETRY_THRES = 0x7c0; |
| 3264 | |
| 3265 | int32_t min_win; |
| 3266 | int32_t win; |
| 3267 | int8_t _adj; |
| 3268 | int16_t adj; |
| 3269 | uint32_t dq; |
| 3270 | |
| 3271 | /*********************************************************************** |
| 3272 | analysis of training results |
| 3273 | ***********************************************************************/ |
| 3274 | err = 0; |
| 3275 | for (slice = 0; slice < SLICE_CNT; slice += 1) { |
| 3276 | k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; |
| 3277 | if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) |
| 3278 | continue; |
| 3279 | |
| 3280 | cs = ddr_csn % 2; |
| 3281 | ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); |
| 3282 | ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX); |
| 3283 | for (i = 0; i < 9; i++) { |
| 3284 | dq = slice * 8 + i; |
| 3285 | if (i == 8) |
| 3286 | _adj = Boardcnf->ch[ch].dm_adj_w[slice]; |
| 3287 | else |
| 3288 | _adj = Boardcnf->ch[ch].dq_adj_w[dq]; |
| 3289 | adj = _f_scale_adj(_adj); |
| 3290 | |
| 3291 | dataL = |
| 3292 | ddr_getval_s(ch, slice, |
| 3293 | _reg_PHY_CLK_WRX_SLAVE_DELAY[i]) + adj; |
| 3294 | ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i], |
| 3295 | dataL); |
| 3296 | wdqdm_dly[ch][cs][slice][i] = dataL; |
| 3297 | } |
| 3298 | ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00); |
| 3299 | dataL = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS); |
| 3300 | wdqdm_st[ch][cs][slice] = dataL; |
| 3301 | min_win = INT_LEAST32_MAX; |
| 3302 | for (i = 0; i <= 8; i++) { |
| 3303 | ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT, |
| 3304 | i); |
| 3305 | |
| 3306 | dataL = |
| 3307 | ddr_getval_s(ch, slice, |
| 3308 | _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS); |
| 3309 | wdqdm_te[ch][cs][slice][i] = dataL; |
| 3310 | dataL = |
| 3311 | ddr_getval_s(ch, slice, |
| 3312 | _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS); |
| 3313 | wdqdm_le[ch][cs][slice][i] = dataL; |
| 3314 | win = |
| 3315 | (int32_t) wdqdm_te[ch][cs][slice][i] - |
| 3316 | wdqdm_le[ch][cs][slice][i]; |
| 3317 | if (min_win > win) |
| 3318 | min_win = win; |
| 3319 | if (dataL >= _par_WDQLVL_RETRY_THRES) |
| 3320 | err = 2; |
| 3321 | } |
| 3322 | wdqdm_win[ch][cs][slice] = min_win; |
| 3323 | ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x01); |
| 3324 | } |
| 3325 | return err; |
| 3326 | } |
| 3327 | |
| 3328 | static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore) |
| 3329 | { |
| 3330 | uint32_t i; |
| 3331 | uint32_t ch, slice; |
| 3332 | uint32_t tgt_cs, src_cs; |
| 3333 | uint32_t tmp_r; |
| 3334 | |
| 3335 | /*********************************************************************** |
| 3336 | copy of training results |
| 3337 | ***********************************************************************/ |
| 3338 | foreach_vch(ch) { |
| 3339 | for (tgt_cs = 0; tgt_cs < CS_CNT; tgt_cs++) { |
| 3340 | for (slice = 0; slice < SLICE_CNT; slice++) { |
| 3341 | ddr_setval_s(ch, slice, |
| 3342 | _reg_PHY_PER_CS_TRAINING_INDEX, |
| 3343 | tgt_cs); |
| 3344 | src_cs = ddr_csn % 2; |
| 3345 | if (!(ch_have_this_cs[1] & (1U << ch))) |
| 3346 | src_cs = 0; |
| 3347 | for (i = 0; i <= 4; i += 4) { |
| 3348 | if (restore) |
| 3349 | tmp_r = |
| 3350 | rdqdm_dly[ch][tgt_cs][slice] |
| 3351 | [i]; |
| 3352 | else |
| 3353 | tmp_r = |
| 3354 | rdqdm_dly[ch][src_cs][slice] |
| 3355 | [i]; |
| 3356 | |
| 3357 | ddr_setval_s(ch, slice, |
| 3358 | _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY |
| 3359 | [i], tmp_r); |
| 3360 | } |
| 3361 | } |
| 3362 | } |
| 3363 | } |
| 3364 | } |
| 3365 | |
| 3366 | static uint32_t wdqdm_man1(void) |
| 3367 | { |
| 3368 | int32_t k; |
| 3369 | uint32_t ch, cs, slice; |
| 3370 | uint32_t ddr_csn; |
| 3371 | uint32_t dataL; |
| 3372 | uint32_t err; |
| 3373 | uint32_t err_flg; |
| 3374 | |
| 3375 | /*********************************************************************** |
| 3376 | manual execution of training |
| 3377 | ***********************************************************************/ |
| 3378 | uint32_t high_dq[DRAM_CH_CNT]; |
| 3379 | uint32_t mr14_csab0_bak[DRAM_CH_CNT]; |
| 3380 | |
| 3381 | foreach_vch(ch) { |
| 3382 | high_dq[ch] = 0; |
| 3383 | for (slice = 0; slice < SLICE_CNT; slice++) { |
| 3384 | k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; |
| 3385 | if (k >= 2) |
| 3386 | high_dq[ch] |= (1U << slice); |
| 3387 | } |
| 3388 | } |
| 3389 | |
| 3390 | if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) |
| 3391 | ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x00); |
| 3392 | |
| 3393 | err = 0; |
| 3394 | /* CLEAR PREV RESULT */ |
| 3395 | for (cs = 0; cs < CS_CNT; cs++) { |
| 3396 | ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs); |
| 3397 | if (((Prr_Product == PRR_PRODUCT_H3) |
| 3398 | && (Prr_Cut > PRR_PRODUCT_11)) |
| 3399 | || (Prr_Product == PRR_PRODUCT_M3N) |
| 3400 | || (Prr_Product == PRR_PRODUCT_V3H)) { |
| 3401 | ddr_setval_ach_as(_reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS, |
| 3402 | 0x01); |
| 3403 | } else { |
| 3404 | ddr_setval_ach_as(_reg_PHY_WDQLVL_CLR_PREV_RESULTS, |
| 3405 | 0x01); |
| 3406 | } |
| 3407 | } |
| 3408 | ddrphy_regif_idle(); |
| 3409 | |
| 3410 | err_flg = 0; |
| 3411 | |
| 3412 | for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { |
| 3413 | if ((Prr_Product == PRR_PRODUCT_H3) |
| 3414 | && (Prr_Cut <= PRR_PRODUCT_11)) { |
| 3415 | foreach_vch(ch) { |
| 3416 | dataL = mmio_read_32(DBSC_DBDFICNT(ch)); |
| 3417 | dataL &= ~(0x00ffU << 16); |
| 3418 | |
| 3419 | if (ddr_csn >= 2) |
| 3420 | k = (high_dq[ch] ^ 0x0f); |
| 3421 | else |
| 3422 | k = high_dq[ch]; |
| 3423 | dataL |= (k << 16); |
| 3424 | mmio_write_32(DBSC_DBDFICNT(ch), dataL); |
| 3425 | ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, k); |
| 3426 | } |
| 3427 | } |
| 3428 | if (((Prr_Product == PRR_PRODUCT_H3) |
| 3429 | && (Prr_Cut <= PRR_PRODUCT_11)) |
| 3430 | || ((Prr_Product == PRR_PRODUCT_M3) |
| 3431 | && (Prr_Cut == PRR_PRODUCT_10))) { |
| 3432 | wdqdm_cp(ddr_csn, 0); |
| 3433 | } |
| 3434 | |
| 3435 | foreach_vch(ch) { |
| 3436 | dataL = |
| 3437 | ddr_getval(ch, |
| 3438 | _reg_PI_MR14_DATA_Fx_CSx[1][ddr_csn]); |
| 3439 | ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0], dataL); |
| 3440 | } |
| 3441 | |
| 3442 | /* KICK WDQLVL */ |
| 3443 | err = swlvl1(ddr_csn, _reg_PI_WDQLVL_CS, _reg_PI_WDQLVL_REQ); |
| 3444 | if (err) |
| 3445 | goto err_exit; |
| 3446 | |
| 3447 | if (ddr_csn == 0) |
| 3448 | foreach_vch(ch) { |
| 3449 | mr14_csab0_bak[ch] = |
| 3450 | ddr_getval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0]); |
| 3451 | } else |
| 3452 | foreach_vch(ch) { |
| 3453 | ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0], |
| 3454 | mr14_csab0_bak[ch]); |
| 3455 | } |
| 3456 | foreach_vch(ch) { |
| 3457 | if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) { |
| 3458 | wdqdm_clr1(ch, ddr_csn); |
| 3459 | continue; |
| 3460 | } |
| 3461 | err = wdqdm_ana1(ch, ddr_csn); |
| 3462 | if (err) |
| 3463 | err_flg |= (1U << (ddr_csn * 4 + ch)); |
| 3464 | ddrphy_regif_idle(); |
| 3465 | } |
| 3466 | } |
| 3467 | err_exit: |
| 3468 | ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x01); |
| 3469 | foreach_vch(ch) { |
| 3470 | dataL = mmio_read_32(DBSC_DBDFICNT(ch)); |
| 3471 | dataL &= ~(0x00ffU << 16); |
| 3472 | mmio_write_32(DBSC_DBDFICNT(ch), dataL); |
| 3473 | ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00); |
| 3474 | } |
| 3475 | return (err_flg | err); |
| 3476 | } |
| 3477 | |
| 3478 | static uint32_t wdqdm_man(void) |
| 3479 | { |
| 3480 | uint32_t err, retry_cnt; |
| 3481 | const uint32_t retry_max = 0x10; |
| 3482 | |
| 3483 | ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, (DBSC_DBTR(11) & 0xFF) + 12); |
| 3484 | if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) |
| 3485 | || (Prr_Product == PRR_PRODUCT_M3N) |
| 3486 | || (Prr_Product == PRR_PRODUCT_V3H)) { |
| 3487 | ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1, |
| 3488 | (DBSC_DBTR(12) & 0xFF) + 1); |
| 3489 | } else { |
| 3490 | ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR, |
| 3491 | (DBSC_DBTR(12) & 0xFF) + 1); |
| 3492 | } |
| 3493 | ddr_setval_ach(_reg_PI_TRFC_F1, (DBSC_DBTR(13) & 0x1FF)); |
| 3494 | |
| 3495 | retry_cnt = 0; |
| 3496 | do { |
| 3497 | if ((Prr_Product == PRR_PRODUCT_H3) |
| 3498 | && (Prr_Cut <= PRR_PRODUCT_11)) { |
| 3499 | err = wdqdm_man1(); |
| 3500 | } else { |
| 3501 | uint32_t ch, ddr_csn, mr14_bkup[4][4]; |
| 3502 | |
| 3503 | ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01); |
| 3504 | ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, |
| 3505 | 0x01); |
| 3506 | if ((Prr_Product == PRR_PRODUCT_M3N) |
| 3507 | || (Prr_Product == PRR_PRODUCT_V3H)) { |
| 3508 | ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, |
| 3509 | 0x0C); |
| 3510 | } else { |
| 3511 | ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x0C); |
| 3512 | } |
| 3513 | dsb_sev(); |
| 3514 | err = wdqdm_man1(); |
| 3515 | foreach_vch(ch) { |
| 3516 | for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { |
| 3517 | mr14_bkup[ch][ddr_csn] = |
| 3518 | ddr_getval(ch, |
| 3519 | _reg_PI_MR14_DATA_Fx_CSx |
| 3520 | [1][ddr_csn]); |
| 3521 | dsb_sev(); |
| 3522 | } |
| 3523 | } |
| 3524 | |
| 3525 | if ((Prr_Product == PRR_PRODUCT_M3N) |
| 3526 | || (Prr_Product == PRR_PRODUCT_V3H)) { |
| 3527 | ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, |
| 3528 | 0x04); |
| 3529 | } else { |
| 3530 | ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x04); |
| 3531 | } |
| 3532 | pvtcode_update(); |
| 3533 | err = wdqdm_man1(); |
| 3534 | foreach_vch(ch) { |
| 3535 | for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { |
| 3536 | mr14_bkup[ch][ddr_csn] = |
| 3537 | (mr14_bkup[ch][ddr_csn] + |
| 3538 | ddr_getval(ch, |
| 3539 | _reg_PI_MR14_DATA_Fx_CSx |
| 3540 | [1][ddr_csn])) / 2; |
| 3541 | ddr_setval(ch, |
| 3542 | _reg_PI_MR14_DATA_Fx_CSx[1] |
| 3543 | [ddr_csn], |
| 3544 | mr14_bkup[ch][ddr_csn]); |
| 3545 | } |
| 3546 | } |
| 3547 | |
| 3548 | ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, |
| 3549 | 0x00); |
| 3550 | if ((Prr_Product == PRR_PRODUCT_M3N) |
| 3551 | || (Prr_Product == PRR_PRODUCT_V3H)) { |
| 3552 | ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, |
| 3553 | 0x00); |
| 3554 | ddr_setval_ach |
| 3555 | (_reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1, |
| 3556 | 0x00); |
| 3557 | ddr_setval_ach |
| 3558 | (_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1, |
| 3559 | 0x00); |
| 3560 | } else { |
| 3561 | ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x00); |
| 3562 | ddr_setval_ach |
| 3563 | (_reg_PI_WDQLVL_VREF_INITIAL_START_POINT, |
| 3564 | 0x00); |
| 3565 | ddr_setval_ach |
| 3566 | (_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT, |
| 3567 | 0x00); |
| 3568 | } |
| 3569 | ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE, |
| 3570 | 0x00); |
| 3571 | |
| 3572 | pvtcode_update2(); |
| 3573 | err = wdqdm_man1(); |
| 3574 | ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00); |
| 3575 | } |
| 3576 | } while (err && (++retry_cnt < retry_max)); |
| 3577 | |
| 3578 | if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) |
| 3579 | || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_10))) { |
| 3580 | wdqdm_cp(0, 1); |
| 3581 | } |
| 3582 | |
| 3583 | return (retry_cnt >= retry_max); |
| 3584 | } |
| 3585 | |
| 3586 | /******************************************************************************* |
| 3587 | * RDQ TRAINING |
| 3588 | ******************************************************************************/ |
| 3589 | static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn) |
| 3590 | { |
| 3591 | int32_t i, k; |
| 3592 | uint32_t cs, slice; |
| 3593 | uint32_t dataL; |
| 3594 | |
| 3595 | /*********************************************************************** |
| 3596 | clr of training results buffer |
| 3597 | ***********************************************************************/ |
| 3598 | cs = ddr_csn % 2; |
| 3599 | dataL = Boardcnf->dqdm_dly_r; |
| 3600 | for (slice = 0; slice < SLICE_CNT; slice++) { |
| 3601 | k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; |
| 3602 | if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) |
| 3603 | continue; |
| 3604 | |
| 3605 | for (i = 0; i <= 8; i++) { |
| 3606 | if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) { |
| 3607 | rdqdm_dly[ch][cs][slice][i] = |
| 3608 | rdqdm_dly[ch][CS_CNT - 1 - cs][slice][i]; |
| 3609 | rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = |
| 3610 | rdqdm_dly[ch][CS_CNT - 1 - cs][slice + |
| 3611 | SLICE_CNT] |
| 3612 | [i]; |
| 3613 | } else { |
| 3614 | rdqdm_dly[ch][cs][slice][i] = dataL; |
| 3615 | rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = dataL; |
| 3616 | } |
| 3617 | rdqdm_le[ch][cs][slice][i] = 0; |
| 3618 | rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0; |
| 3619 | rdqdm_te[ch][cs][slice][i] = 0; |
| 3620 | rdqdm_te[ch][cs][slice + SLICE_CNT][i] = 0; |
| 3621 | rdqdm_nw[ch][cs][slice][i] = 0; |
| 3622 | rdqdm_nw[ch][cs][slice + SLICE_CNT][i] = 0; |
| 3623 | } |
| 3624 | rdqdm_st[ch][cs][slice] = 0; |
| 3625 | rdqdm_win[ch][cs][slice] = 0; |
| 3626 | } |
| 3627 | } |
| 3628 | |
| 3629 | static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) |
| 3630 | { |
| 3631 | int32_t i, k; |
| 3632 | uint32_t cs, slice; |
| 3633 | uint32_t dataL; |
| 3634 | uint32_t err; |
| 3635 | int8_t _adj; |
| 3636 | int16_t adj; |
| 3637 | uint32_t dq; |
| 3638 | |
| 3639 | /*********************************************************************** |
| 3640 | analysis of training results |
| 3641 | ***********************************************************************/ |
| 3642 | err = 0; |
| 3643 | for (slice = 0; slice < SLICE_CNT; slice++) { |
| 3644 | int32_t min_win; |
| 3645 | int32_t win; |
| 3646 | uint32_t rdq_status_obs_select; |
| 3647 | k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; |
| 3648 | if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) |
| 3649 | continue; |
| 3650 | |
| 3651 | cs = ddr_csn % 2; |
| 3652 | ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); |
| 3653 | ddrphy_regif_idle(); |
| 3654 | |
| 3655 | ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX); |
| 3656 | ddrphy_regif_idle(); |
| 3657 | |
| 3658 | for (i = 0; i <= 8; i++) { |
| 3659 | dq = slice * 8 + i; |
| 3660 | if (i == 8) |
| 3661 | _adj = Boardcnf->ch[ch].dm_adj_r[slice]; |
| 3662 | else |
| 3663 | _adj = Boardcnf->ch[ch].dq_adj_r[dq]; |
| 3664 | |
| 3665 | adj = _f_scale_adj(_adj); |
| 3666 | |
| 3667 | dataL = |
| 3668 | ddr_getval_s(ch, slice, |
| 3669 | _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + |
| 3670 | adj; |
| 3671 | ddr_setval_s(ch, slice, |
| 3672 | _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], |
| 3673 | dataL); |
| 3674 | rdqdm_dly[ch][cs][slice][i] = dataL; |
| 3675 | |
| 3676 | dataL = |
| 3677 | ddr_getval_s(ch, slice, |
| 3678 | _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + |
| 3679 | adj; |
| 3680 | ddr_setval_s(ch, slice, |
| 3681 | _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], |
| 3682 | dataL); |
| 3683 | rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = dataL; |
| 3684 | } |
| 3685 | min_win = INT_LEAST32_MAX; |
| 3686 | for (i = 0; i <= 8; i++) { |
| 3687 | dataL = |
| 3688 | ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS); |
| 3689 | rdqdm_st[ch][cs][slice] = dataL; |
| 3690 | rdqdm_st[ch][cs][slice + SLICE_CNT] = dataL; |
| 3691 | /* k : rise/fall */ |
| 3692 | for (k = 0; k < 2; k++) { |
| 3693 | if (i == 8) { |
| 3694 | rdq_status_obs_select = 16 + 8 * k; |
| 3695 | } else { |
| 3696 | rdq_status_obs_select = i + k * 8; |
| 3697 | } |
| 3698 | ddr_setval_s(ch, slice, |
| 3699 | _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT, |
| 3700 | rdq_status_obs_select); |
| 3701 | |
| 3702 | dataL = |
| 3703 | ddr_getval_s(ch, slice, |
| 3704 | _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); |
| 3705 | rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] = |
| 3706 | dataL; |
| 3707 | |
| 3708 | dataL = |
| 3709 | ddr_getval_s(ch, slice, |
| 3710 | _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); |
| 3711 | rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] = |
| 3712 | dataL; |
| 3713 | |
| 3714 | dataL = |
| 3715 | ddr_getval_s(ch, slice, |
| 3716 | _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS); |
| 3717 | rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] = |
| 3718 | dataL; |
| 3719 | |
| 3720 | win = |
| 3721 | (int32_t) rdqdm_te[ch][cs][slice + |
| 3722 | SLICE_CNT * |
| 3723 | k][i] - |
| 3724 | rdqdm_le[ch][cs][slice + SLICE_CNT * k][i]; |
| 3725 | if (i != 8) { |
| 3726 | if (min_win > win) |
| 3727 | min_win = win; |
| 3728 | } |
| 3729 | } |
| 3730 | } |
| 3731 | rdqdm_win[ch][cs][slice] = min_win; |
| 3732 | if (min_win <= 0) { |
| 3733 | err = 2; |
| 3734 | } |
| 3735 | } |
| 3736 | return (err); |
| 3737 | } |
| 3738 | |
| 3739 | static uint32_t rdqdm_man1(void) |
| 3740 | { |
| 3741 | uint32_t ch; |
| 3742 | uint32_t ddr_csn; |
| 3743 | uint32_t err; |
| 3744 | |
| 3745 | /*********************************************************************** |
| 3746 | manual execution of training |
| 3747 | ***********************************************************************/ |
| 3748 | err = 0; |
| 3749 | |
| 3750 | for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { |
| 3751 | /* KICK RDQLVL */ |
| 3752 | err = swlvl1(ddr_csn, _reg_PI_RDLVL_CS, _reg_PI_RDLVL_REQ); |
| 3753 | if (err) |
| 3754 | goto err_exit; |
| 3755 | |
| 3756 | foreach_vch(ch) { |
| 3757 | if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) { |
| 3758 | rdqdm_clr1(ch, ddr_csn); |
| 3759 | ddrphy_regif_idle(); |
| 3760 | continue; |
| 3761 | } |
| 3762 | err = rdqdm_ana1(ch, ddr_csn); |
| 3763 | ddrphy_regif_idle(); |
| 3764 | if (err) |
| 3765 | goto err_exit; |
| 3766 | } |
| 3767 | } |
| 3768 | err_exit: |
| 3769 | return (err); |
| 3770 | } |
| 3771 | |
| 3772 | static uint32_t rdqdm_man(void) |
| 3773 | { |
| 3774 | uint32_t err, retry_cnt; |
| 3775 | const uint32_t retry_max = 0x01; |
| 3776 | |
| 3777 | ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE, |
| 3778 | 0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, |
| 3779 | _reg_PHY_DQ_TSEL_ENABLE)); |
| 3780 | ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE, |
| 3781 | 0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, |
| 3782 | _reg_PHY_DQS_TSEL_ENABLE)); |
| 3783 | ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT, |
| 3784 | 0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, |
| 3785 | _reg_PHY_DQ_TSEL_SELECT)); |
| 3786 | ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT, |
| 3787 | 0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, |
| 3788 | _reg_PHY_DQS_TSEL_SELECT)); |
| 3789 | |
| 3790 | retry_cnt = 0; |
| 3791 | do { |
| 3792 | err = rdqdm_man1(); |
| 3793 | ddrphy_regif_idle(); |
| 3794 | } while (err && (++retry_cnt < retry_max)); |
| 3795 | ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE, |
| 3796 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, |
| 3797 | _reg_PHY_DQ_TSEL_ENABLE)); |
| 3798 | ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE, |
| 3799 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, |
| 3800 | _reg_PHY_DQS_TSEL_ENABLE)); |
| 3801 | ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT, |
| 3802 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, |
| 3803 | _reg_PHY_DQ_TSEL_SELECT)); |
| 3804 | ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT, |
| 3805 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, |
| 3806 | _reg_PHY_DQS_TSEL_SELECT)); |
| 3807 | |
| 3808 | return (retry_cnt >= retry_max); |
| 3809 | } |
| 3810 | |
| 3811 | /******************************************************************************* |
| 3812 | * rx offset calibration |
| 3813 | ******************************************************************************/ |
| 3814 | static int32_t _find_change(uint64_t val, uint32_t dir) |
| 3815 | { |
| 3816 | int32_t i; |
| 3817 | uint32_t startval; |
| 3818 | uint32_t curval; |
| 3819 | const uint32_t VAL_END = 0x3f; |
| 3820 | |
| 3821 | if (dir == 0) { |
| 3822 | startval = (val & 0x01); |
| 3823 | for (i = 1; i <= VAL_END; i++) { |
| 3824 | curval = (val >> i) & 0x01; |
| 3825 | if (curval != startval) |
| 3826 | return (i); |
| 3827 | } |
| 3828 | return (VAL_END); |
| 3829 | } else { |
| 3830 | startval = (val >> dir) & 0x01; |
| 3831 | for (i = dir - 1; i >= 0; i--) { |
| 3832 | curval = (val >> i) & 0x01; |
| 3833 | if (curval != startval) |
| 3834 | return (i); |
| 3835 | } |
| 3836 | return (0); |
| 3837 | } |
| 3838 | } |
| 3839 | |
| 3840 | static uint32_t _rx_offset_cal_updn(uint32_t code) |
| 3841 | { |
| 3842 | const uint32_t CODE_MAX = 0x40; |
| 3843 | uint32_t tmp; |
| 3844 | |
| 3845 | if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { |
| 3846 | if (code == 0) |
| 3847 | tmp = (1U << 6) | (CODE_MAX - 1); |
| 3848 | else if (code <= 0x20) |
| 3849 | tmp = |
| 3850 | ((CODE_MAX - 1 - |
| 3851 | (0x20 - code) * 2) << 6) | (CODE_MAX - 1); |
| 3852 | else |
| 3853 | tmp = |
| 3854 | ((CODE_MAX - 1) << 6) | (CODE_MAX - 1 - |
| 3855 | (code - 0x20) * 2); |
| 3856 | } else { |
| 3857 | if (code == 0) |
| 3858 | tmp = (1U << 6) | (CODE_MAX - 1); |
| 3859 | else |
| 3860 | tmp = (code << 6) | (CODE_MAX - code); |
| 3861 | } |
| 3862 | return tmp; |
| 3863 | } |
| 3864 | |
| 3865 | /* #define RX_OFFSET_FAST */ |
| 3866 | static uint32_t rx_offset_cal(void) |
| 3867 | { |
| 3868 | uint32_t index; |
| 3869 | uint32_t code; |
| 3870 | const uint32_t CODE_MAX = 0x40; |
| 3871 | const uint32_t CODE_STEP = 2; |
| 3872 | uint32_t ch, slice; |
| 3873 | uint32_t tmp; |
| 3874 | uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT]; |
| 3875 | uint64_t val[DRAM_CH_CNT][SLICE_CNT][_reg_PHY_RX_CAL_X_NUM]; |
| 3876 | #ifdef RX_OFFSET_FAST |
| 3877 | uint32_t adr_st; |
| 3878 | adr_st = ddr_regdef_adr(_reg_PHY_RX_CAL_X[0]); |
| 3879 | #endif |
| 3880 | ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01); |
| 3881 | ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01); |
| 3882 | foreach_vch(ch) { |
| 3883 | for (slice = 0; slice < SLICE_CNT; slice++) { |
| 3884 | for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) { |
| 3885 | val[ch][slice][index] = 0; |
| 3886 | } |
| 3887 | } |
| 3888 | } |
| 3889 | |
| 3890 | for (code = 0; code < CODE_MAX / CODE_STEP; code++) { |
| 3891 | tmp = _rx_offset_cal_updn(code * CODE_STEP); |
| 3892 | #ifdef RX_OFFSET_FAST |
| 3893 | tmp = tmp | (tmp << 16); |
| 3894 | for (index = 0; index < (_reg_PHY_RX_CAL_X_NUM + 1) / 2; |
| 3895 | index++) { |
| 3896 | for (slice = 0; slice < 4; slice++) |
| 3897 | reg_ddrphy_write_a(adr_st + 0x80 * slice + |
| 3898 | index, tmp); |
| 3899 | } |
| 3900 | #else |
| 3901 | for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) { |
| 3902 | ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp); |
| 3903 | } |
| 3904 | #endif |
| 3905 | dsb_sev(); |
| 3906 | ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *) tmp_ach_as); |
| 3907 | |
| 3908 | foreach_vch(ch) { |
| 3909 | for (slice = 0; slice < SLICE_CNT; slice++) { |
| 3910 | tmp = tmp_ach_as[ch][slice]; |
| 3911 | for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; |
| 3912 | index++) { |
| 3913 | if (tmp & (1U << index)) { |
| 3914 | val[ch][slice][index] |= |
| 3915 | (1ULL << code); |
| 3916 | } else { |
| 3917 | val[ch][slice][index] &= |
| 3918 | ~(1ULL << code); |
| 3919 | } |
| 3920 | } |
| 3921 | } |
| 3922 | } |
| 3923 | } |
| 3924 | foreach_vch(ch) { |
| 3925 | for (slice = 0; slice < SLICE_CNT; slice++) { |
| 3926 | for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) { |
| 3927 | uint64_t tmpval; |
| 3928 | int32_t lsb, msb; |
| 3929 | tmpval = val[ch][slice][index]; |
| 3930 | lsb = _find_change(tmpval, 0); |
| 3931 | msb = |
| 3932 | _find_change(tmpval, |
| 3933 | (CODE_MAX / CODE_STEP) - 1); |
| 3934 | tmp = (lsb + msb) >> 1; |
| 3935 | |
| 3936 | tmp = _rx_offset_cal_updn(tmp * CODE_STEP); |
| 3937 | ddr_setval_s(ch, slice, |
| 3938 | _reg_PHY_RX_CAL_X[index], tmp); |
| 3939 | } |
| 3940 | } |
| 3941 | } |
| 3942 | ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00); |
| 3943 | ddr_setval_ach_as(_reg_PHY_IE_MODE, |
| 3944 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, |
| 3945 | _reg_PHY_IE_MODE)); |
| 3946 | |
| 3947 | return 0; |
| 3948 | } |
| 3949 | |
| 3950 | static uint32_t rx_offset_cal_hw(void) |
| 3951 | { |
| 3952 | uint32_t ch, slice; |
| 3953 | uint32_t retry; |
| 3954 | uint32_t complete; |
| 3955 | uint32_t tmp; |
| 3956 | uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT]; |
| 3957 | |
| 3958 | ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01); |
| 3959 | ddr_setval_ach_as(_reg_PHY_RX_CAL_X[9], 0x00); |
| 3960 | ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00); |
| 3961 | ddr_setval_ach_as(_reg_PHY_RX_CAL_SAMPLE_WAIT, 0x0f); |
| 3962 | |
| 3963 | retry = 0; |
| 3964 | while (retry < 4096) { |
| 3965 | if ((retry & 0xff) == 0) { |
| 3966 | ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01); |
| 3967 | } |
| 3968 | foreach_vch(ch) |
| 3969 | for (slice = 0; slice < SLICE_CNT; slice++) |
| 3970 | tmp_ach_as[ch][slice] = |
| 3971 | ddr_getval_s(ch, slice, _reg_PHY_RX_CAL_X[9]); |
| 3972 | |
| 3973 | complete = 1; |
| 3974 | foreach_vch(ch) { |
| 3975 | for (slice = 0; slice < SLICE_CNT; slice++) { |
| 3976 | tmp = tmp_ach_as[ch][slice]; |
| 3977 | tmp = (tmp & 0x3f) + ((tmp >> 6) & 0x3f); |
| 3978 | if (((Prr_Product == PRR_PRODUCT_H3) |
| 3979 | && (Prr_Cut > PRR_PRODUCT_11)) |
| 3980 | || (Prr_Product == PRR_PRODUCT_M3N) |
| 3981 | || (Prr_Product == PRR_PRODUCT_V3H)) { |
| 3982 | if (tmp != 0x3E) |
| 3983 | complete = 0; |
| 3984 | } else { |
| 3985 | if (tmp != 0x40) |
| 3986 | complete = 0; |
| 3987 | } |
| 3988 | } |
| 3989 | } |
| 3990 | if (complete) |
| 3991 | break; |
| 3992 | |
| 3993 | retry++; |
| 3994 | } |
| 3995 | ddr_setval_ach_as(_reg_PHY_IE_MODE, |
| 3996 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, |
| 3997 | _reg_PHY_IE_MODE)); |
| 3998 | |
| 3999 | return (complete == 0); |
| 4000 | } |
| 4001 | |
| 4002 | /******************************************************************************* |
| 4003 | * adjust rddqs latency |
| 4004 | ******************************************************************************/ |
| 4005 | static void adjust_rddqs_latency(void) |
| 4006 | { |
| 4007 | uint32_t ch, slice; |
| 4008 | uint32_t dly; |
| 4009 | uint32_t maxlatx2; |
| 4010 | uint32_t tmp; |
| 4011 | uint32_t rdlat_adjx2[SLICE_CNT]; |
| 4012 | foreach_vch(ch) { |
| 4013 | maxlatx2 = 0; |
| 4014 | for (slice = 0; slice < SLICE_CNT; slice++) { |
| 4015 | ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, |
| 4016 | 0x00); |
| 4017 | |
| 4018 | dly = |
| 4019 | ddr_getval_s(ch, slice, |
| 4020 | _reg_PHY_RDDQS_GATE_SLAVE_DELAY); |
| 4021 | tmp = |
| 4022 | ddr_getval_s(ch, slice, |
| 4023 | _reg_PHY_RDDQS_LATENCY_ADJUST); |
| 4024 | /* note gate_slave_delay[9] is always 0 */ |
| 4025 | tmp = (tmp << 1) + (dly >> 8); |
| 4026 | rdlat_adjx2[slice] = tmp; |
| 4027 | if (maxlatx2 < tmp) |
| 4028 | maxlatx2 = tmp; |
| 4029 | } |
| 4030 | maxlatx2 = ((maxlatx2 + 1) >> 1) << 1; |
| 4031 | for (slice = 0; slice < SLICE_CNT; slice++) { |
| 4032 | tmp = maxlatx2 - rdlat_adjx2[slice]; |
| 4033 | tmp = (tmp >> 1); |
| 4034 | if (tmp) { |
| 4035 | ddr_setval_s(ch, slice, _reg_PHY_RPTR_UPDATE, |
| 4036 | ddr_getval_s(ch, slice, |
| 4037 | _reg_PHY_RPTR_UPDATE) |
| 4038 | + 1); |
| 4039 | } |
| 4040 | } |
| 4041 | } |
| 4042 | } |
| 4043 | |
| 4044 | /******************************************************************************* |
| 4045 | * adjust wpath latency |
| 4046 | ******************************************************************************/ |
| 4047 | static void adjust_wpath_latency(void) |
| 4048 | { |
| 4049 | uint32_t ch, cs, slice; |
| 4050 | uint32_t dly; |
| 4051 | uint32_t wpath_add; |
| 4052 | const uint32_t _par_EARLY_THRESHOLD_VAL = 0x180; |
| 4053 | |
| 4054 | foreach_vch(ch) { |
| 4055 | for (slice = 0; slice < SLICE_CNT; slice += 1) { |
| 4056 | for (cs = 0; cs < CS_CNT; cs++) { |
| 4057 | ddr_setval_s(ch, slice, |
| 4058 | _reg_PHY_PER_CS_TRAINING_INDEX, |
| 4059 | cs); |
| 4060 | ddr_getval_s(ch, slice, |
| 4061 | _reg_PHY_PER_CS_TRAINING_INDEX); |
| 4062 | dly = |
| 4063 | ddr_getval_s(ch, slice, |
| 4064 | _reg_PHY_CLK_WRDQS_SLAVE_DELAY); |
| 4065 | if (dly <= _par_EARLY_THRESHOLD_VAL) |
| 4066 | continue; |
| 4067 | |
| 4068 | wpath_add = |
| 4069 | ddr_getval_s(ch, slice, |
| 4070 | _reg_PHY_WRITE_PATH_LAT_ADD); |
| 4071 | ddr_setval_s(ch, slice, |
| 4072 | _reg_PHY_WRITE_PATH_LAT_ADD, |
| 4073 | wpath_add - 1); |
| 4074 | } |
| 4075 | } |
| 4076 | } |
| 4077 | } |
| 4078 | |
| 4079 | /******************************************************************************* |
| 4080 | * DDR Initialize entry |
| 4081 | ******************************************************************************/ |
| 4082 | int32_t rcar_dram_init(void) |
| 4083 | { |
| 4084 | uint32_t ch, cs; |
| 4085 | uint32_t dataL; |
| 4086 | uint32_t bus_mbps, bus_mbpsdiv; |
| 4087 | uint32_t tmp_tccd; |
| 4088 | uint32_t failcount; |
| 4089 | |
| 4090 | /*********************************************************************** |
| 4091 | Thermal sensor setting |
| 4092 | ***********************************************************************/ |
| 4093 | dataL = *((volatile uint32_t *)CPG_MSTPSR5); |
| 4094 | if (dataL & BIT22) { /* case THS/TSC Standby */ |
| 4095 | dataL &= ~(BIT22); |
| 4096 | *((volatile uint32_t *)CPG_CPGWPR) = ~dataL; |
| 4097 | *((volatile uint32_t *)CPG_SMSTPCR5) = dataL; |
| 4098 | while ((BIT22) & *((volatile uint32_t *)CPG_MSTPSR5)) ; /* wait bit=0 */ |
| 4099 | } |
| 4100 | |
| 4101 | /* THCTR Bit6: PONM=0 , Bit0: THSST=0 */ |
| 4102 | dataL = (*((volatile uint32_t *)THS1_THCTR)) & 0xFFFFFFBE; |
| 4103 | *((volatile uint32_t *)THS1_THCTR) = dataL; |
| 4104 | |
| 4105 | /*********************************************************************** |
| 4106 | Judge product and cut |
| 4107 | ***********************************************************************/ |
| 4108 | #ifdef RCAR_DDR_FIXED_LSI_TYPE |
| 4109 | #if(RCAR_LSI==RCAR_AUTO) |
| 4110 | Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; |
| 4111 | Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; |
| 4112 | #else /* RCAR_LSI */ |
| 4113 | #ifndef RCAR_LSI_CUT |
| 4114 | Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; |
| 4115 | #endif /* RCAR_LSI_CUT */ |
| 4116 | #endif /* RCAR_LSI */ |
| 4117 | #else /* RCAR_DDR_FIXED_LSI_TYPE */ |
| 4118 | Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; |
| 4119 | Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; |
| 4120 | #endif /* RCAR_DDR_FIXED_LSI_TYPE */ |
| 4121 | |
| 4122 | if (Prr_Product == PRR_PRODUCT_H3) { |
| 4123 | if (Prr_Cut <= PRR_PRODUCT_11) { |
| 4124 | pDDR_REGDEF_TBL = (uint32_t *) & DDR_REGDEF_TBL[0][0]; |
| 4125 | } else { |
| 4126 | pDDR_REGDEF_TBL = (uint32_t *) & DDR_REGDEF_TBL[2][0]; |
| 4127 | } |
| 4128 | } else if (Prr_Product == PRR_PRODUCT_M3) { |
| 4129 | pDDR_REGDEF_TBL = (uint32_t *) & DDR_REGDEF_TBL[1][0]; |
| 4130 | } else if ((Prr_Product == PRR_PRODUCT_M3N) |
| 4131 | || (Prr_Product == PRR_PRODUCT_V3H)) { |
| 4132 | pDDR_REGDEF_TBL = (uint32_t *) & DDR_REGDEF_TBL[3][0]; |
| 4133 | } else { |
| 4134 | FATAL_MSG("DDR:Unknown Product"); |
| 4135 | return 0xff; |
| 4136 | } |
| 4137 | |
| 4138 | if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) |
| 4139 | || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20))) { |
| 4140 | /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ |
| 4141 | } else { |
| 4142 | mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); |
| 4143 | } |
| 4144 | |
| 4145 | /*********************************************************************** |
| 4146 | Judge board type |
| 4147 | ***********************************************************************/ |
| 4148 | _cnf_BOARDTYPE = boardcnf_get_brd_type(); |
| 4149 | if (_cnf_BOARDTYPE >= BOARDNUM) { |
| 4150 | FATAL_MSG("DDR:Unknown Board"); |
| 4151 | return 0xff; |
| 4152 | } |
| 4153 | Boardcnf = (struct _boardcnf *)&boardcnfs[_cnf_BOARDTYPE]; |
| 4154 | |
| 4155 | /* RCAR_DRAM_SPLIT_2CH (2U) */ |
| 4156 | #if RCAR_DRAM_SPLIT == 2 |
| 4157 | /*********************************************************************** |
| 4158 | H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split |
| 4159 | ***********************************************************************/ |
| 4160 | if ((Prr_Product == PRR_PRODUCT_H3) && (Boardcnf->phyvalid == 0x05)) { |
| 4161 | mmio_write_32(DBSC_DBMEMSWAPCONF0, 0x00000006); |
| 4162 | ddr_phyvalid = 0x03; |
| 4163 | } else { |
| 4164 | ddr_phyvalid = Boardcnf->phyvalid; |
| 4165 | } |
| 4166 | #else /* RCAR_DRAM_SPLIT_2CH */ |
| 4167 | ddr_phyvalid = Boardcnf->phyvalid; |
| 4168 | #endif /* RCAR_DRAM_SPLIT_2CH */ |
| 4169 | |
| 4170 | max_density = 0; |
| 4171 | |
| 4172 | for (cs = 0; cs < CS_CNT; cs++) { |
| 4173 | ch_have_this_cs[cs] = 0; |
| 4174 | } |
| 4175 | |
| 4176 | foreach_ech(ch) |
| 4177 | for (cs = 0; cs < CS_CNT; cs++) |
| 4178 | ddr_density[ch][cs] = 0xff; |
| 4179 | |
| 4180 | foreach_vch(ch) { |
| 4181 | for (cs = 0; cs < CS_CNT; cs++) { |
| 4182 | dataL = Boardcnf->ch[ch].ddr_density[cs]; |
| 4183 | ddr_density[ch][cs] = dataL; |
| 4184 | |
| 4185 | if (dataL == 0xff) |
| 4186 | continue; |
| 4187 | if (dataL > max_density) |
| 4188 | max_density = dataL; |
| 4189 | if ((cs == 1) && (Prr_Product == PRR_PRODUCT_H3) |
| 4190 | && (Prr_Cut <= PRR_PRODUCT_11)) |
| 4191 | continue; |
| 4192 | ch_have_this_cs[cs] |= (1U << ch); |
| 4193 | } |
| 4194 | } |
| 4195 | |
| 4196 | /*********************************************************************** |
| 4197 | Judge board clock frequency (in MHz) |
| 4198 | ***********************************************************************/ |
| 4199 | boardcnf_get_brd_clk(_cnf_BOARDTYPE, &brd_clk, &brd_clkdiv); |
| 4200 | if ((brd_clk / brd_clkdiv) > 25) { |
| 4201 | brd_clkdiva = 1; |
| 4202 | } else { |
| 4203 | brd_clkdiva = 0; |
| 4204 | } |
| 4205 | |
| 4206 | /*********************************************************************** |
| 4207 | Judge ddr operating frequency clock(in Mbps) |
| 4208 | ***********************************************************************/ |
| 4209 | boardcnf_get_ddr_mbps(_cnf_BOARDTYPE, &ddr_mbps, &ddr_mbpsdiv); |
| 4210 | |
| 4211 | ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1)); |
| 4212 | |
| 4213 | ddr_mul = |
| 4214 | CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk, |
| 4215 | brd_clkdiv * (brd_clkdiva + 1)); |
| 4216 | |
| 4217 | /*********************************************************************** |
| 4218 | Adjust tccd |
| 4219 | ***********************************************************************/ |
| 4220 | dataL = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13; |
| 4221 | switch (dataL) { |
| 4222 | case 0: |
| 4223 | bus_mbps = brd_clk * 0x60 * 2; |
| 4224 | bus_mbpsdiv = brd_clkdiv * 1; |
| 4225 | break; |
| 4226 | case 1: |
| 4227 | bus_mbps = brd_clk * 0x50 * 2; |
| 4228 | bus_mbpsdiv = brd_clkdiv * 1; |
| 4229 | break; |
| 4230 | case 2: |
| 4231 | bus_mbps = brd_clk * 0x40 * 2; |
| 4232 | bus_mbpsdiv = brd_clkdiv * 1; |
| 4233 | break; |
| 4234 | case 3: |
| 4235 | bus_mbps = brd_clk * 0x60 * 2; |
| 4236 | bus_mbpsdiv = brd_clkdiv * 2; |
| 4237 | break; |
| 4238 | default: |
| 4239 | bus_mbps = brd_clk * 0x60 * 2; |
| 4240 | bus_mbpsdiv = brd_clkdiv * 2; |
| 4241 | break; |
| 4242 | } |
| 4243 | tmp_tccd = CLK_DIV(ddr_mbps * 8, ddr_mbpsdiv, bus_mbps, bus_mbpsdiv); |
| 4244 | if (8 * ddr_mbps * bus_mbpsdiv != tmp_tccd * bus_mbps * ddr_mbpsdiv) |
| 4245 | tmp_tccd = tmp_tccd + 1; |
| 4246 | |
| 4247 | if (tmp_tccd < 8) |
| 4248 | ddr_tccd = 8; |
| 4249 | else |
| 4250 | ddr_tccd = tmp_tccd; |
| 4251 | |
| 4252 | NOTICE("BL2: DDR%d(%s)", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION); |
| 4253 | |
| 4254 | MSG_LF("Start\n"); |
| 4255 | |
| 4256 | /*********************************************************************** |
| 4257 | PLL Setting |
| 4258 | ***********************************************************************/ |
| 4259 | pll3_control(1); |
| 4260 | |
| 4261 | /*********************************************************************** |
| 4262 | initialize DDR |
| 4263 | ***********************************************************************/ |
| 4264 | dataL = init_ddr(); |
| 4265 | if (dataL == ddr_phyvalid) { |
| 4266 | failcount = 0; |
| 4267 | } else { |
| 4268 | failcount = 1; |
| 4269 | } |
| 4270 | |
| 4271 | NOTICE("..%d\n", failcount); |
| 4272 | |
| 4273 | foreach_vch(ch) |
| 4274 | mmio_write_32(DBSC_DBPDLK(ch), 0x00000000); |
| 4275 | if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) |
| 4276 | || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20))) { |
| 4277 | /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ |
| 4278 | } else { |
| 4279 | mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); |
| 4280 | } |
| 4281 | |
| 4282 | if (failcount == 0) { |
| 4283 | return INITDRAM_OK; |
| 4284 | } else { |
| 4285 | return INITDRAM_NG; |
| 4286 | } |
| 4287 | } |
| 4288 | |
| 4289 | void pvtcode_update(void) |
| 4290 | { |
| 4291 | uint32_t ch; |
| 4292 | uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init; |
| 4293 | int32_t pvtp_tmp, pvtn_tmp; |
| 4294 | |
| 4295 | foreach_vch(ch) { |
| 4296 | pvtn_init = (tcal.tcomp_cal[ch] & 0xFC0) >> 6; |
| 4297 | pvtp_init = (tcal.tcomp_cal[ch] & 0x03F) >> 0; |
| 4298 | |
| 4299 | if (8912 * pvtp_init > 44230) { |
| 4300 | pvtp_tmp = (5000 + 8912 * pvtp_init - 44230) / 10000; |
| 4301 | } else { |
| 4302 | pvtp_tmp = |
| 4303 | -((-(5000 + 8912 * pvtp_init - 44230)) / 10000); |
| 4304 | } |
| 4305 | pvtn_tmp = (5000 + 5776 * pvtn_init + 30280) / 10000; |
| 4306 | |
| 4307 | pvtn[ch] = pvtn_tmp + pvtn_init; |
| 4308 | pvtp[ch] = pvtp_tmp + pvtp_init; |
| 4309 | |
| 4310 | if (pvtn[ch] > 63) { |
| 4311 | pvtn[ch] = 63; |
| 4312 | pvtp[ch] = |
| 4313 | (pvtp_tmp) * (63 - 6 * pvtn_tmp - |
| 4314 | pvtn_init) / (pvtn_tmp) + |
| 4315 | 6 * pvtp_tmp + pvtp_init; |
| 4316 | } |
| 4317 | if ((Prr_Product == PRR_PRODUCT_H3) |
| 4318 | && (Prr_Cut <= PRR_PRODUCT_11)) { |
| 4319 | reg_ddrphy_write(ch, |
| 4320 | ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), |
| 4321 | pvtp[ch] | (pvtn[ch] << 6) | (tcal. |
| 4322 | tcomp_cal |
| 4323 | [ch] & |
| 4324 | 0xfffff000)); |
| 4325 | reg_ddrphy_write(ch, |
| 4326 | ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), |
| 4327 | pvtp[ch] | (pvtn[ch] << 6) | (tcal. |
| 4328 | tcomp_cal |
| 4329 | [ch] & |
| 4330 | 0xfffff000)); |
| 4331 | reg_ddrphy_write(ch, |
| 4332 | ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), |
| 4333 | pvtp[ch] | (pvtn[ch] << 6) | (tcal. |
| 4334 | tcomp_cal |
| 4335 | [ch] & |
| 4336 | 0xfffff000)); |
| 4337 | reg_ddrphy_write(ch, |
| 4338 | ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), |
| 4339 | pvtp[ch] | (pvtn[ch] << 6) | (tcal. |
| 4340 | tcomp_cal |
| 4341 | [ch] & |
| 4342 | 0xfffff000)); |
| 4343 | reg_ddrphy_write(ch, |
| 4344 | ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), |
| 4345 | pvtp[ch] | (pvtn[ch] << 6) | (tcal. |
| 4346 | tcomp_cal |
| 4347 | [ch] & |
| 4348 | 0xfffff000)); |
| 4349 | } else { |
| 4350 | reg_ddrphy_write(ch, |
| 4351 | ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), |
| 4352 | pvtp[ch] | (pvtn[ch] << 6) | |
| 4353 | 0x00035000); |
| 4354 | reg_ddrphy_write(ch, |
| 4355 | ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), |
| 4356 | pvtp[ch] | (pvtn[ch] << 6) | |
| 4357 | 0x00015000); |
| 4358 | reg_ddrphy_write(ch, |
| 4359 | ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), |
| 4360 | pvtp[ch] | (pvtn[ch] << 6) | |
| 4361 | 0x00015000); |
| 4362 | |
| 4363 | reg_ddrphy_write(ch, |
| 4364 | ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), |
| 4365 | pvtp[ch] | (pvtn[ch] << 6) | |
| 4366 | 0x00015000); |
| 4367 | reg_ddrphy_write(ch, |
| 4368 | ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), |
| 4369 | pvtp[ch] | (pvtn[ch] << 6) | |
| 4370 | 0x00015000); |
| 4371 | } |
| 4372 | } |
| 4373 | } |
| 4374 | |
| 4375 | void pvtcode_update2(void) |
| 4376 | { |
| 4377 | uint32_t ch; |
| 4378 | foreach_vch(ch) { |
| 4379 | reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), |
| 4380 | tcal.init_cal[ch] | 0x00020000); |
| 4381 | reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), |
| 4382 | tcal.init_cal[ch]); |
| 4383 | reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), |
| 4384 | tcal.init_cal[ch]); |
| 4385 | reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), |
| 4386 | tcal.init_cal[ch]); |
| 4387 | reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), |
| 4388 | tcal.init_cal[ch]); |
| 4389 | } |
| 4390 | } |
| 4391 | |
| 4392 | void ddr_padcal_tcompensate_getinit(uint32_t override) |
| 4393 | { |
| 4394 | uint32_t ch; |
| 4395 | uint32_t dataL; |
| 4396 | uint32_t pvtp, pvtn; |
| 4397 | |
| 4398 | tcal.init_temp = 0; |
| 4399 | for (ch = 0; ch < 4; ch++) { |
| 4400 | tcal.init_cal[ch] = 0; |
| 4401 | tcal.tcomp_cal[ch] = 0; |
| 4402 | } |
| 4403 | |
| 4404 | foreach_vch(ch) { |
| 4405 | tcal.init_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]); |
| 4406 | tcal.tcomp_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]); |
| 4407 | } |
| 4408 | |
| 4409 | if (!override) { |
| 4410 | dataL = *((volatile uint32_t *)THS1_TEMP); |
| 4411 | if (dataL < 2800) { |
| 4412 | tcal.init_temp = |
| 4413 | (143 * (int32_t) dataL - 359000) / 1000; |
| 4414 | } else { |
| 4415 | tcal.init_temp = |
| 4416 | (121 * (int32_t) dataL - 296300) / 1000; |
| 4417 | } |
| 4418 | |
| 4419 | foreach_vch(ch) { |
| 4420 | pvtp = (tcal.init_cal[ch] >> 0) & 0x000003F; |
| 4421 | pvtn = (tcal.init_cal[ch] >> 6) & 0x000003F; |
| 4422 | if ((int32_t) pvtp > |
| 4423 | ((tcal.init_temp * 29 - 3625) / 1000)) |
| 4424 | pvtp = |
| 4425 | (int32_t) pvtp + |
| 4426 | ((3625 - tcal.init_temp * 29) / 1000); |
| 4427 | else |
| 4428 | pvtp = 0; |
| 4429 | |
| 4430 | if ((int32_t) pvtn > |
| 4431 | ((tcal.init_temp * 54 - 6750) / 1000)) |
| 4432 | pvtn = |
| 4433 | (int32_t) pvtn + |
| 4434 | ((6750 - tcal.init_temp * 54) / 1000); |
| 4435 | else |
| 4436 | pvtn = 0; |
| 4437 | |
| 4438 | if ((Prr_Product == PRR_PRODUCT_H3) |
| 4439 | && (Prr_Cut <= PRR_PRODUCT_11)) { |
| 4440 | tcal.init_cal[ch] = |
| 4441 | (tcal. |
| 4442 | init_cal[ch] & 0xfffff000) | (pvtn << 6) | |
| 4443 | (pvtp); |
| 4444 | } else { |
| 4445 | tcal.init_cal[ch] = |
| 4446 | 0x00015000 | (pvtn << 6) | (pvtp); |
| 4447 | } |
| 4448 | } |
| 4449 | tcal.init_temp = 125; |
| 4450 | } |
| 4451 | } |
| 4452 | |
| 4453 | #ifndef ddr_qos_init_setting |
| 4454 | /* for QoS init */ |
| 4455 | uint8_t get_boardcnf_phyvalid(void) |
| 4456 | { |
| 4457 | /* return Boardcnf->phyvalid; */ |
| 4458 | return ddr_phyvalid; |
| 4459 | } |
| 4460 | #endif /* ddr_qos_init_setting */ |
| 4461 | |
| 4462 | /******************************************************************************* |
| 4463 | * END |
| 4464 | ******************************************************************************/ |