Joel Hutton | 2691bc6 | 2017-12-12 15:47:55 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <assert_macros.S> |
| 9 | #include <asm_macros.S> |
| 10 | |
| 11 | .globl amu_group0_cnt_read_internal |
| 12 | .globl amu_group0_cnt_write_internal |
| 13 | .globl amu_group1_cnt_read_internal |
| 14 | .globl amu_group1_cnt_write_internal |
| 15 | .globl amu_group1_set_evtype_internal |
| 16 | |
| 17 | /* |
| 18 | * uint64_t amu_group0_cnt_read_internal(int idx); |
| 19 | * |
| 20 | * Given `idx`, read the corresponding AMU counter |
| 21 | * and return it in `r0`. |
| 22 | */ |
| 23 | func amu_group0_cnt_read_internal |
| 24 | #if ENABLE_ASSERTIONS |
| 25 | /* `idx` should be between [0, 3] */ |
| 26 | mov r1, r0 |
| 27 | lsr r1, r1, #2 |
| 28 | cmp r1, #0 |
| 29 | ASM_ASSERT(eq) |
| 30 | #endif |
| 31 | |
| 32 | /* |
| 33 | * Given `idx` calculate address of ldcopr16/bx lr instruction pair |
| 34 | * in the table below. |
| 35 | */ |
| 36 | adr r1, 1f |
| 37 | lsl r0, r0, #3 /* each ldcopr16/bx lr sequence is 8 bytes */ |
| 38 | add r1, r1, r0 |
| 39 | bx r1 |
| 40 | 1: |
| 41 | ldcopr16 r0, r1, AMEVCNTR00 /* index 0 */ |
| 42 | bx lr |
| 43 | ldcopr16 r0, r1, AMEVCNTR01 /* index 1 */ |
| 44 | bx lr |
| 45 | ldcopr16 r0, r1, AMEVCNTR02 /* index 2 */ |
| 46 | bx lr |
| 47 | ldcopr16 r0, r1, AMEVCNTR03 /* index 3 */ |
| 48 | bx lr |
| 49 | endfunc amu_group0_cnt_read_internal |
| 50 | |
| 51 | /* |
| 52 | * void amu_group0_cnt_write_internal(int idx, uint64_t val); |
| 53 | * |
| 54 | * Given `idx`, write `val` to the corresponding AMU counter. |
| 55 | */ |
| 56 | func amu_group0_cnt_write_internal |
| 57 | #if ENABLE_ASSERTIONS |
| 58 | /* `idx` should be between [0, 3] */ |
| 59 | mov r2, r0 |
| 60 | lsr r2, r2, #2 |
| 61 | cmp r2, #0 |
| 62 | ASM_ASSERT(eq) |
| 63 | #endif |
| 64 | |
| 65 | /* |
| 66 | * Given `idx` calculate address of stcopr16/bx lr instruction pair |
| 67 | * in the table below. |
| 68 | */ |
| 69 | adr r2, 1f |
| 70 | lsl r0, r0, #3 /* each stcopr16/bx lr sequence is 8 bytes */ |
| 71 | add r2, r2, r0 |
| 72 | bx r2 |
| 73 | |
| 74 | 1: |
| 75 | stcopr16 r0,r1, AMEVCNTR00 /* index 0 */ |
| 76 | bx lr |
| 77 | stcopr16 r0,r1, AMEVCNTR01 /* index 1 */ |
| 78 | bx lr |
| 79 | stcopr16 r0,r1, AMEVCNTR02 /* index 2 */ |
| 80 | bx lr |
| 81 | stcopr16 r0,r1, AMEVCNTR03 /* index 3 */ |
| 82 | bx lr |
| 83 | endfunc amu_group0_cnt_write_internal |
| 84 | |
| 85 | /* |
| 86 | * uint64_t amu_group1_cnt_read_internal(int idx); |
| 87 | * |
| 88 | * Given `idx`, read the corresponding AMU counter |
| 89 | * and return it in `r0`. |
| 90 | */ |
| 91 | func amu_group1_cnt_read_internal |
| 92 | #if ENABLE_ASSERTIONS |
| 93 | /* `idx` should be between [0, 15] */ |
| 94 | mov r2, r0 |
| 95 | lsr r2, r2, #4 |
| 96 | cmp r2, #0 |
| 97 | ASM_ASSERT(eq) |
| 98 | #endif |
| 99 | |
| 100 | /* |
| 101 | * Given `idx` calculate address of ldcopr16/bx lr instruction pair |
| 102 | * in the table below. |
| 103 | */ |
| 104 | adr r1, 1f |
| 105 | lsl r0, r0, #3 /* each ldcopr16/bx lr sequence is 8 bytes */ |
| 106 | add r1, r1, r0 |
| 107 | bx r1 |
| 108 | |
| 109 | 1: |
| 110 | ldcopr16 r0,r1, AMEVCNTR10 /* index 0 */ |
| 111 | bx lr |
| 112 | ldcopr16 r0,r1, AMEVCNTR11 /* index 1 */ |
| 113 | bx lr |
| 114 | ldcopr16 r0,r1, AMEVCNTR12 /* index 2 */ |
| 115 | bx lr |
| 116 | ldcopr16 r0,r1, AMEVCNTR13 /* index 3 */ |
| 117 | bx lr |
| 118 | ldcopr16 r0,r1, AMEVCNTR14 /* index 4 */ |
| 119 | bx lr |
| 120 | ldcopr16 r0,r1, AMEVCNTR15 /* index 5 */ |
| 121 | bx lr |
| 122 | ldcopr16 r0,r1, AMEVCNTR16 /* index 6 */ |
| 123 | bx lr |
| 124 | ldcopr16 r0,r1, AMEVCNTR17 /* index 7 */ |
| 125 | bx lr |
| 126 | ldcopr16 r0,r1, AMEVCNTR18 /* index 8 */ |
| 127 | bx lr |
| 128 | ldcopr16 r0,r1, AMEVCNTR19 /* index 9 */ |
| 129 | bx lr |
| 130 | ldcopr16 r0,r1, AMEVCNTR1A /* index 10 */ |
| 131 | bx lr |
| 132 | ldcopr16 r0,r1, AMEVCNTR1B /* index 11 */ |
| 133 | bx lr |
| 134 | ldcopr16 r0,r1, AMEVCNTR1C /* index 12 */ |
| 135 | bx lr |
| 136 | ldcopr16 r0,r1, AMEVCNTR1D /* index 13 */ |
| 137 | bx lr |
| 138 | ldcopr16 r0,r1, AMEVCNTR1E /* index 14 */ |
| 139 | bx lr |
| 140 | ldcopr16 r0,r1, AMEVCNTR1F /* index 15 */ |
| 141 | bx lr |
| 142 | endfunc amu_group1_cnt_read_internal |
| 143 | |
| 144 | /* |
| 145 | * void amu_group1_cnt_write_internal(int idx, uint64_t val); |
| 146 | * |
| 147 | * Given `idx`, write `val` to the corresponding AMU counter. |
| 148 | */ |
| 149 | func amu_group1_cnt_write_internal |
| 150 | #if ENABLE_ASSERTIONS |
| 151 | /* `idx` should be between [0, 15] */ |
| 152 | mov r2, r0 |
| 153 | lsr r2, r2, #4 |
| 154 | cmp r2, #0 |
| 155 | ASM_ASSERT(eq) |
| 156 | #endif |
| 157 | |
| 158 | /* |
| 159 | * Given `idx` calculate address of ldcopr16/bx lr instruction pair |
| 160 | * in the table below. |
| 161 | */ |
| 162 | adr r2, 1f |
| 163 | lsl r0, r0, #3 /* each stcopr16/bx lr sequence is 8 bytes */ |
| 164 | add r2, r2, r0 |
| 165 | bx r2 |
| 166 | |
| 167 | 1: |
| 168 | stcopr16 r0,r1, AMEVCNTR10 /* index 0 */ |
| 169 | bx lr |
| 170 | stcopr16 r0,r1, AMEVCNTR11 /* index 1 */ |
| 171 | bx lr |
| 172 | stcopr16 r0,r1, AMEVCNTR12 /* index 2 */ |
| 173 | bx lr |
| 174 | stcopr16 r0,r1, AMEVCNTR13 /* index 3 */ |
| 175 | bx lr |
| 176 | stcopr16 r0,r1, AMEVCNTR14 /* index 4 */ |
| 177 | bx lr |
| 178 | stcopr16 r0,r1, AMEVCNTR15 /* index 5 */ |
| 179 | bx lr |
| 180 | stcopr16 r0,r1, AMEVCNTR16 /* index 6 */ |
| 181 | bx lr |
| 182 | stcopr16 r0,r1, AMEVCNTR17 /* index 7 */ |
| 183 | bx lr |
| 184 | stcopr16 r0,r1, AMEVCNTR18 /* index 8 */ |
| 185 | bx lr |
| 186 | stcopr16 r0,r1, AMEVCNTR19 /* index 9 */ |
| 187 | bx lr |
| 188 | stcopr16 r0,r1, AMEVCNTR1A /* index 10 */ |
| 189 | bx lr |
| 190 | stcopr16 r0,r1, AMEVCNTR1B /* index 11 */ |
| 191 | bx lr |
| 192 | stcopr16 r0,r1, AMEVCNTR1C /* index 12 */ |
| 193 | bx lr |
| 194 | stcopr16 r0,r1, AMEVCNTR1D /* index 13 */ |
| 195 | bx lr |
| 196 | stcopr16 r0,r1, AMEVCNTR1E /* index 14 */ |
| 197 | bx lr |
| 198 | stcopr16 r0,r1, AMEVCNTR1F /* index 15 */ |
| 199 | bx lr |
| 200 | endfunc amu_group1_cnt_write_internal |
| 201 | |
| 202 | /* |
| 203 | * void amu_group1_set_evtype_internal(int idx, unsigned int val); |
| 204 | * |
| 205 | * Program the AMU event type register indexed by `idx` |
| 206 | * with the value `val`. |
| 207 | */ |
| 208 | func amu_group1_set_evtype_internal |
| 209 | #if ENABLE_ASSERTIONS |
| 210 | /* `idx` should be between [0, 15] */ |
| 211 | mov r2, r0 |
| 212 | lsr r2, r2, #4 |
| 213 | cmp r2, #0 |
| 214 | ASM_ASSERT(eq) |
| 215 | |
| 216 | /* val should be between [0, 65535] */ |
| 217 | mov r2, r1 |
| 218 | lsr r2, r2, #16 |
| 219 | cmp r2, #0 |
| 220 | ASM_ASSERT(eq) |
| 221 | #endif |
| 222 | |
| 223 | /* |
| 224 | * Given `idx` calculate address of stcopr/bx lr instruction pair |
| 225 | * in the table below. |
| 226 | */ |
| 227 | adr r2, 1f |
| 228 | lsl r0, r0, #3 /* each stcopr/bx lr sequence is 8 bytes */ |
| 229 | add r2, r2, r0 |
| 230 | bx r2 |
| 231 | |
| 232 | 1: |
| 233 | stcopr r0, AMEVTYPER10 /* index 0 */ |
| 234 | bx lr |
| 235 | stcopr r0, AMEVTYPER11 /* index 1 */ |
| 236 | bx lr |
| 237 | stcopr r0, AMEVTYPER12 /* index 2 */ |
| 238 | bx lr |
| 239 | stcopr r0, AMEVTYPER13 /* index 3 */ |
| 240 | bx lr |
| 241 | stcopr r0, AMEVTYPER14 /* index 4 */ |
| 242 | bx lr |
| 243 | stcopr r0, AMEVTYPER15 /* index 5 */ |
| 244 | bx lr |
| 245 | stcopr r0, AMEVTYPER16 /* index 6 */ |
| 246 | bx lr |
| 247 | stcopr r0, AMEVTYPER17 /* index 7 */ |
| 248 | bx lr |
| 249 | stcopr r0, AMEVTYPER18 /* index 8 */ |
| 250 | bx lr |
| 251 | stcopr r0, AMEVTYPER19 /* index 9 */ |
| 252 | bx lr |
| 253 | stcopr r0, AMEVTYPER1A /* index 10 */ |
| 254 | bx lr |
| 255 | stcopr r0, AMEVTYPER1B /* index 11 */ |
| 256 | bx lr |
| 257 | stcopr r0, AMEVTYPER1C /* index 12 */ |
| 258 | bx lr |
| 259 | stcopr r0, AMEVTYPER1D /* index 13 */ |
| 260 | bx lr |
| 261 | stcopr r0, AMEVTYPER1E /* index 14 */ |
| 262 | bx lr |
| 263 | stcopr r0, AMEVTYPER1F /* index 15 */ |
| 264 | bx lr |
| 265 | endfunc amu_group1_set_evtype_internal |