blob: aa987b3feb4217c9d9afb975bbfee025445e6b7d [file] [log] [blame]
Bryan O'Donoghue967ed972018-05-25 17:35:09 +01001/*
2 * Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#include <arch.h>
7#include <asm_macros.S>
8#include <assert_macros.S>
9#include <imx_uart.h>
10#include <platform_def.h>
11
12 .globl imx_crash_uart_init
13 .globl imx_crash_uart_putc
14
15 /* -----------------------------------------------
16 * int imx_crash_uart_init(uintptr_t base_addr,
17 * unsigned int uart_clk, unsigned int baud_rate)
18 * Function to initialize the console without a
19 * C Runtime to print debug information. This
20 * function will be accessed by console_init and
21 * crash reporting.
22 * In: r0 - console base address
23 * r1 - Uart clock in Hz
24 * r2 - Baud rate
25 * Out: return 1 on success else 0 on error
26 * Clobber list : r1, r2, r3, r4
27 * -----------------------------------------------
28 */
29func imx_crash_uart_init
30 /* Free up r1 as a scratch reg */
31 mov r4, r0
32 mov r0, r1
33
34 /* Reset UART via CR2 */
35 add r1, r4, #IMX_UART_CR2_OFFSET
36 movs r3, #0
37 str r3, [r4, #IMX_UART_CR2_OFFSET]
38
39 /* Wait for reset complete */
40__wait_cr2_reset:
41 ldr r3, [r1, #0]
42 ands r3, #IMX_UART_CR2_SRST
43 beq __wait_cr2_reset
44
45 /* Enable UART */
46 movs r3, #IMX_UART_CR1_UARTEN
47 mov r1, r2
48 str r3, [r4, #IMX_UART_CR1_OFFSET]
49
50 /*
51 * Ignore RTC/CTS - disable reset
52 * Magic value #16423 =>
53 * IMX_UART_CR2_IRTS | IMX_UART_CR2_WS | IMX_UART_CR2_TXEN | IMX_UART_CR2_RXEN | IMX_UART_CR2_SRST
54 */
55 movw r3, #16423
56 str r3, [r4, #IMX_UART_CR2_OFFSET]
57
58 /*
59 * No parity, autobaud detect-old, rxdmuxsel=1 (fixed i.mx7)
60 * Magic value => #132
61 * IMX_UART_CR3_ADNIMP | IMX_UART_CR3_RXDMUXSEL
62 */
63 movs r3, #132
64 str r3, [r4, #IMX_UART_CR3_OFFSET]
65
66 /*
67 * Set CTS FIFO trigger to 32 bytes bits 15:10
68 * Magic value => #32768
69 * FIFO trigger bitmask 100000
70 * */
71 mov r3, #32768
72 str r3, [r4, #IMX_UART_CR4_OFFSET]
73
74 /*
75 * TX/RX-thresh = 2 bytes, DCE (bit6 = 0), refclk @24MHz / 4
76 * Magic value #2562
77 * IMX_UART_FCR_TXTL(TX_RX_THRESH) | IMX_UART_FCR_RXTL(TX_RX_THRESH) | IMX_UART_FCR_RFDIV2
78 */
79 #ifdef IMX_UART_DTE
80 movw r3, #2626
81 #else
82 movw r3, #2562
83 #endif
84 str r3, [r4, #IMX_UART_FCR_OFFSET]
85
86 /* This BIR should be set to 0x0F prior to writing the BMR */
87 movs r3, #15
88 str r3, [r4, #IMX_UART_BIR_OFFSET]
89
90 /* Hard-code to 115200 @ 24 MHz */
91 movs r0, #104
92 str r0, [r4, #IMX_UART_BMR_OFFSET]
93
94 /* Indicate success */
95 movs r0, #1
96 bx lr
97endfunc imx_crash_uart_init
98
99 /* --------------------------------------------------------
100 * int imx_crash_uart_putc(int c, uintptr_t base_addr)
101 * Function to output a character over the console. It
102 * returns the character printed on success or -1 on error.
103 * In : r0 - character to be printed
104 * r1 - console base address
105 * Out : return -1 on error else return character.
106 * Clobber list : r2
107 * --------------------------------------------------------
108 */
109func imx_crash_uart_putc
110 /* Output specified character to UART shift-register */
111 str r0, [r1, #IMX_UART_TXD_OFFSET]
112
113 /* Wait for transmit IMX_UART_STAT2_OFFSET.IMX_UART_STAT2_TXDC == 1 */
114__putc_spin_ready:
115 ldr r2, [r1, #IMX_UART_STAT2_OFFSET]
116 ands r2, #IMX_UART_STAT2_TXDC
117 beq __putc_spin_ready
118
119 /* Transmit complete do we need to fixup \n to \n\r */
120 cmp r0, #10
121 beq __putc_fixup_lf
122
123 /* No fixup necessary - exit here */
124 movs r0, #0
125 bx lr
126
127 /* Fixup \n to \n\r */
128__putc_fixup_lf:
129 movs r0, #13
130 b imx_crash_uart_putc
131endfunc imx_crash_uart_putc