blob: 739e2b9f355ed52f846c7c6b2f1fe7a1431393ca [file] [log] [blame]
Jacky Bai8e2109d2023-05-25 09:35:44 +08001/*
2 * Copyright 2022-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <arch_helpers.h>
9#include <plat/common/platform.h>
10
11const unsigned char imx_power_domain_tree_desc[] = {
12 PWR_DOMAIN_AT_MAX_LVL,
13 PLATFORM_CLUSTER_COUNT,
14 PLATFORM_CLUSTER0_CORE_COUNT,
15};
16
17const unsigned char *plat_get_power_domain_tree_desc(void)
18{
19 return imx_power_domain_tree_desc;
20}
21
22/*
23 * Only one cluster is planned for i.MX9 family, no need
24 * to consider the cluster id
25 */
26int plat_core_pos_by_mpidr(u_register_t mpidr)
27{
28 unsigned int cpu_id;
29
30 mpidr &= MPIDR_AFFINITY_MASK;
31
32 if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) {
33 return -1;
34 }
35
36 cpu_id = MPIDR_AFFLVL1_VAL(mpidr);
37
38 return cpu_id;
39}