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Soby Mathew3b5156e2017-10-05 12:27:33 +01001/*
Madhukar Pappireddy8afa6672024-07-18 18:03:42 -05002 * Copyright (c) 2017-2024, ARM Limited and Contributors. All rights reserved.
Soby Mathew3b5156e2017-10-05 12:27:33 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00006#ifndef PLAT_LD_S
7#define PLAT_LD_S
Soby Mathew3b5156e2017-10-05 12:27:33 +01008
Madhukar Pappireddy8afa6672024-07-18 18:03:42 -05009#include <lib/xlat_tables/xlat_tables_defs.h>
10
11MEMORY {
12 EL3_SEC_DRAM (rw): ORIGIN = ARM_EL3_TZC_DRAM1_BASE, LENGTH = ARM_EL3_TZC_DRAM1_SIZE
13}
14
15SECTIONS
16{
17 . = ARM_EL3_TZC_DRAM1_BASE;
18 ASSERT(. == ALIGN(PAGE_SIZE),
19 "ARM_EL3_TZC_DRAM_BASE address is not aligned on a page boundary.")
20 .el3_tzc_dram (NOLOAD) : ALIGN(PAGE_SIZE) {
21 __PLAT_SPMC_SHMEM_DATASTORE_START__ = .;
22 *(.arm_spmc_shmem_datastore)
23 __PLAT_SPMC_SHMEM_DATASTORE_END__ = .;
24 __EL3_SEC_DRAM_START__ = .;
25 *(.arm_el3_tzc_dram)
26#if SEPARATE_SIMD_SECTION
27 . = ALIGN(16);
28 *(.simd_context)
29#endif
30 __EL3_SEC_DRAM_UNALIGNED_END__ = .;
31
32 . = ALIGN(PAGE_SIZE);
33 __EL3_SEC_DRAM_END__ = .;
34 } >EL3_SEC_DRAM
35}
Ambroise Vincente8b10e22019-07-16 17:19:38 +010036
37#if RECLAIM_INIT_CODE
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000038#include <plat/arm/common/arm_reclaim_init.ld.S>
Ambroise Vincente8b10e22019-07-16 17:19:38 +010039#endif /* RECLAIM_INIT_CODE */
Soby Mathew3b5156e2017-10-05 12:27:33 +010040
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000041#endif /* PLAT_LD_S */