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Antonio Nino Diazae6779e2017-11-06 14:49:04 +00001/*
2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __PLATFORM_DEF_H__
8#define __PLATFORM_DEF_H__
9
10#include <arch.h>
11#include <common_def.h>
12#include <tbbr_img_def.h>
13#include <utils_def.h>
14
15#include "../rpi3_hw.h"
16
17/* Special value used to verify platform parameters from BL2 to BL31 */
18#define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978)
19
20#define PLATFORM_STACK_SIZE ULL(0x1000)
21
22#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
23#define PLATFORM_CLUSTER_COUNT U(1)
24#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
25#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
26
27#define RPI3_PRIMARY_CPU U(0)
28
29#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
30#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
31 PLATFORM_CORE_COUNT)
32
33#define PLAT_MAX_RET_STATE U(1)
34#define PLAT_MAX_OFF_STATE U(2)
35
36/* Local power state for power domains in Run state. */
37#define PLAT_LOCAL_STATE_RUN U(0)
38/* Local power state for retention. Valid only for CPU power domains */
39#define PLAT_LOCAL_STATE_RET U(1)
40/*
41 * Local power state for OFF/power-down. Valid for CPU and cluster power
42 * domains.
43 */
44#define PLAT_LOCAL_STATE_OFF U(2)
45
46/*
47 * Macros used to parse state information from State-ID if it is using the
48 * recommended encoding for State-ID.
49 */
50#define PLAT_LOCAL_PSTATE_WIDTH U(4)
51#define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1)
52
53/*
54 * Some data must be aligned on the biggest cache line size in the platform.
55 * This is known only to the platform as it might have a combination of
56 * integrated and external caches.
57 */
58#define CACHE_WRITEBACK_SHIFT U(6)
59#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
60
61/*
62 * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", and
63 * secure DRAM. Note that this is all actually DRAM with different names,
64 * there is no Secure RAM in the Raspberry Pi 3.
65 */
66#define SEC_ROM_BASE ULL(0x00000000)
Ying-Chun Liu (PaulLiu)9128df62018-07-04 02:26:48 +080067#define SEC_ROM_SIZE ULL(0x00020000)
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000068
69/* FIP placed after ROM to append it to BL1 with very little padding. */
Ying-Chun Liu (PaulLiu)9128df62018-07-04 02:26:48 +080070#define PLAT_RPI3_FIP_BASE ULL(0x00020000)
71#define PLAT_RPI3_FIP_MAX_SIZE ULL(0x001E0000)
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000072
Antonio Nino Diaz50c5a9e2018-07-15 11:56:33 +010073/* We have 16M of memory reserved starting at 256M */
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000074#define SEC_SRAM_BASE ULL(0x10000000)
75#define SEC_SRAM_SIZE ULL(0x00100000)
76
77#define SEC_DRAM0_BASE ULL(0x10100000)
Antonio Nino Diaz50c5a9e2018-07-15 11:56:33 +010078#define SEC_DRAM0_SIZE ULL(0x00F00000)
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000079/* End of reserved memory */
80
Antonio Nino Diaz50c5a9e2018-07-15 11:56:33 +010081#define NS_DRAM0_BASE ULL(0x11000000)
82#define NS_DRAM0_SIZE ULL(0x01000000)
83
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000084/*
85 * BL33 entrypoint.
86 */
87#define PLAT_RPI3_NS_IMAGE_OFFSET NS_DRAM0_BASE
88#define PLAT_RPI3_NS_IMAGE_MAX_SIZE NS_DRAM0_SIZE
89
90/*
91 * I/O registers.
92 */
93#define DEVICE0_BASE RPI3_IO_BASE
94#define DEVICE0_SIZE RPI3_IO_SIZE
95
96/*
97 * Arm TF lives in SRAM, partition it here
98 */
99#define SHARED_RAM_BASE SEC_SRAM_BASE
100#define SHARED_RAM_SIZE ULL(0x00001000)
101
102#define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE)
103#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE)
104
105/*
106 * Mailbox to control the secondary cores.All secondary cores are held in a wait
107 * loop in cold boot. To release them perform the following steps (plus any
108 * additional barriers that may be needed):
109 *
110 * uint64_t *entrypoint = (uint64_t *)PLAT_RPI3_TM_ENTRYPOINT;
111 * *entrypoint = ADDRESS_TO_JUMP_TO;
112 *
113 * uint64_t *mbox_entry = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE;
114 * mbox_entry[cpu_id] = PLAT_RPI3_TM_HOLD_STATE_GO;
115 *
116 * sev();
117 */
118#define PLAT_RPI3_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE
119
Antonio Nino Diazbc297332018-07-14 01:22:43 +0100120/* The secure entry point to be used on warm reset by all CPUs. */
Antonio Nino Diazae6779e2017-11-06 14:49:04 +0000121#define PLAT_RPI3_TM_ENTRYPOINT PLAT_RPI3_TRUSTED_MAILBOX_BASE
122#define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8)
123
Antonio Nino Diazbc297332018-07-14 01:22:43 +0100124/* Hold entries for each CPU. */
Antonio Nino Diazae6779e2017-11-06 14:49:04 +0000125#define PLAT_RPI3_TM_HOLD_BASE (PLAT_RPI3_TM_ENTRYPOINT + \
126 PLAT_RPI3_TM_ENTRYPOINT_SIZE)
127#define PLAT_RPI3_TM_HOLD_ENTRY_SIZE ULL(8)
128#define PLAT_RPI3_TM_HOLD_SIZE (PLAT_RPI3_TM_HOLD_ENTRY_SIZE * \
129 PLATFORM_CORE_COUNT)
130
131#define PLAT_RPI3_TRUSTED_MAILBOX_SIZE (PLAT_RPI3_TM_ENTRYPOINT_SIZE + \
132 PLAT_RPI3_TM_HOLD_SIZE)
133
134#define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0)
135#define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1)
136
137/*
138 * BL1 specific defines.
139 *
140 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
141 * addresses.
142 *
143 * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using
144 * the current BL1 RW debug size plus a little space for growth.
145 */
146#define PLAT_MAX_BL1_RW_SIZE ULL(0x12000)
147
148#define BL1_RO_BASE SEC_ROM_BASE
149#define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE)
150#define BL1_RW_BASE (BL1_RW_LIMIT - PLAT_MAX_BL1_RW_SIZE)
151#define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
152
153/*
154 * BL2 specific defines.
155 *
156 * Put BL2 just below BL31. BL2_BASE is calculated using the current BL2 debug
157 * size plus a little space for growth.
158 */
159#define PLAT_MAX_BL2_SIZE ULL(0x2C000)
160
161#define BL2_BASE (BL2_LIMIT - PLAT_MAX_BL2_SIZE)
162#define BL2_LIMIT BL31_BASE
163
164/*
165 * BL31 specific defines.
166 *
167 * Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the
168 * current BL31 debug size plus a little space for growth.
169 */
170#define PLAT_MAX_BL31_SIZE ULL(0x20000)
171
172#define BL31_BASE (BL31_LIMIT - PLAT_MAX_BL31_SIZE)
173#define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
174#define BL31_PROGBITS_LIMIT BL1_RW_BASE
175
176/*
177 * BL32 specific defines.
178 *
179 * BL32 can execute from Secure SRAM or Secure DRAM.
180 */
181#define BL32_SRAM_BASE BL_RAM_BASE
182#define BL32_SRAM_LIMIT BL31_BASE
183#define BL32_DRAM_BASE SEC_DRAM0_BASE
184#define BL32_DRAM_LIMIT (SEC_DRAM0_BASE + SEC_DRAM0_SIZE)
185
Ying-Chun Liu (PaulLiu)d9f76e62018-06-10 02:00:27 +0800186#ifdef SPD_opteed
187/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
188#define RPI3_OPTEE_PAGEABLE_LOAD_SIZE 0x080000 /* 512KB */
189#define RPI3_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - \
190 RPI3_OPTEE_PAGEABLE_LOAD_SIZE)
191#endif
192
Antonio Nino Diazae6779e2017-11-06 14:49:04 +0000193#define SEC_SRAM_ID 0
194#define SEC_DRAM_ID 1
195
196#if RPI3_BL32_RAM_LOCATION_ID == SEC_SRAM_ID
197# define BL32_MEM_BASE BL_RAM_BASE
198# define BL32_MEM_SIZE BL_RAM_SIZE
199# define BL32_BASE BL32_SRAM_BASE
200# define BL32_LIMIT BL32_SRAM_LIMIT
201#elif RPI3_BL32_RAM_LOCATION_ID == SEC_DRAM_ID
202# define BL32_MEM_BASE SEC_DRAM0_BASE
203# define BL32_MEM_SIZE SEC_DRAM0_SIZE
204# define BL32_BASE BL32_DRAM_BASE
205# define BL32_LIMIT BL32_DRAM_LIMIT
206#else
207# error "Unsupported RPI3_BL32_RAM_LOCATION_ID value"
208#endif
209#define BL32_SIZE (BL32_LIMIT - BL32_BASE)
210
211#ifdef SPD_none
212#undef BL32_BASE
213#endif /* SPD_none */
214
215/*
216 * Other memory-related defines.
217 */
218#define ADDR_SPACE_SIZE (ULL(1) << 32)
219
220#define MAX_MMAP_REGIONS U(8)
221#define MAX_XLAT_TABLES U(4)
222
223#define MAX_IO_DEVICES U(3)
224#define MAX_IO_HANDLES U(4)
225
226/*
227 * Serial-related constants.
228 */
229#define PLAT_RPI3_UART_BASE RPI3_MINI_UART_BASE
230#define PLAT_RPI3_UART_CLK_IN_HZ RPI3_MINI_UART_CLK_IN_HZ
231#define PLAT_RPI3_UART_BAUDRATE ULL(115200)
232
233/*
234 * System counter
235 */
236#define SYS_COUNTER_FREQ_IN_TICKS ULL(19200000)
237
238#endif /* __PLATFORM_DEF_H__ */