Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2018 Marvell International Ltd. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * https://spdx.org/licenses |
| 6 | */ |
| 7 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 8 | #ifndef MARVELL_DEF_H |
| 9 | #define MARVELL_DEF_H |
Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 10 | |
Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 11 | #include <platform_def.h> |
Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 12 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 13 | #include <arch.h> |
| 14 | #include <common/tbbr/tbbr_img_def.h> |
Remi Pommarel | 7459e74 | 2019-07-14 20:34:28 +0200 | [diff] [blame] | 15 | #include <lib/xlat_tables/xlat_tables_v2.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 16 | #include <plat/common/common_def.h> |
Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 17 | |
| 18 | /****************************************************************************** |
| 19 | * Definitions common to all MARVELL standard platforms |
| 20 | *****************************************************************************/ |
| 21 | |
| 22 | /* Special value used to verify platform parameters from BL2 to BL31 */ |
| 23 | #define MARVELL_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL |
| 24 | |
| 25 | |
| 26 | #define MARVELL_CACHE_WRITEBACK_SHIFT 6 |
| 27 | |
| 28 | /* |
| 29 | * Macros mapping the MPIDR Affinity levels to MARVELL Platform Power levels. |
| 30 | * The power levels have a 1:1 mapping with the MPIDR affinity levels. |
| 31 | */ |
| 32 | #define MARVELL_PWR_LVL0 MPIDR_AFFLVL0 |
| 33 | #define MARVELL_PWR_LVL1 MPIDR_AFFLVL1 |
| 34 | #define MARVELL_PWR_LVL2 MPIDR_AFFLVL2 |
| 35 | |
| 36 | /* |
| 37 | * Macros for local power states in Marvell platforms encoded by |
| 38 | * State-ID field within the power-state parameter. |
| 39 | */ |
| 40 | /* Local power state for power domains in Run state. */ |
| 41 | #define MARVELL_LOCAL_STATE_RUN 0 |
| 42 | /* Local power state for retention. Valid only for CPU power domains */ |
| 43 | #define MARVELL_LOCAL_STATE_RET 1 |
| 44 | /* |
| 45 | * Local power state for OFF/power-down. Valid for CPU |
| 46 | * and cluster power domains |
| 47 | */ |
| 48 | #define MARVELL_LOCAL_STATE_OFF 2 |
| 49 | |
Konstantin Porotchkin | 5f8630b | 2020-06-19 17:48:48 +0200 | [diff] [blame] | 50 | /* This leaves a gap between end of DRAM and start of ROM block */ |
| 51 | #define MARVELL_TRUSTED_DRAM_SIZE 0x80000 /* 512 KB */ |
| 52 | |
Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 53 | /* The first 4KB of Trusted SRAM are used as shared memory */ |
Konstantin Porotchkin | 5f8630b | 2020-06-19 17:48:48 +0200 | [diff] [blame] | 54 | #define MARVELL_SHARED_RAM_BASE PLAT_MARVELL_ATF_BASE |
Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 55 | #define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ |
| 56 | |
| 57 | /* The remaining Trusted SRAM is used to load the BL images */ |
| 58 | #define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \ |
| 59 | MARVELL_SHARED_RAM_SIZE) |
Konstantin Porotchkin | 5f8630b | 2020-06-19 17:48:48 +0200 | [diff] [blame] | 60 | #define MARVELL_BL_RAM_SIZE (MARVELL_TRUSTED_DRAM_SIZE - \ |
Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 61 | MARVELL_SHARED_RAM_SIZE) |
| 62 | /* Non-shared DRAM */ |
| 63 | #define MARVELL_DRAM_BASE ULL(0x0) |
| 64 | #define MARVELL_DRAM_SIZE ULL(0x80000000) |
| 65 | #define MARVELL_DRAM_END (MARVELL_DRAM_BASE + \ |
| 66 | MARVELL_DRAM_SIZE - 1) |
| 67 | |
Marcin Wojtas | 0c60c2f | 2018-03-21 09:59:59 +0100 | [diff] [blame] | 68 | #define MARVELL_IRQ_PIC0 28 |
Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 69 | #define MARVELL_IRQ_SEC_PHY_TIMER 29 |
| 70 | |
| 71 | #define MARVELL_IRQ_SEC_SGI_0 8 |
| 72 | #define MARVELL_IRQ_SEC_SGI_1 9 |
| 73 | #define MARVELL_IRQ_SEC_SGI_2 10 |
| 74 | #define MARVELL_IRQ_SEC_SGI_3 11 |
| 75 | #define MARVELL_IRQ_SEC_SGI_4 12 |
| 76 | #define MARVELL_IRQ_SEC_SGI_5 13 |
| 77 | #define MARVELL_IRQ_SEC_SGI_6 14 |
| 78 | #define MARVELL_IRQ_SEC_SGI_7 15 |
| 79 | |
Konstantin Porotchkin | 841ffeb | 2019-04-15 16:29:08 +0300 | [diff] [blame] | 80 | #ifdef SPD_opteed |
| 81 | /* |
| 82 | * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to |
| 83 | * load/authenticate the trusted os extra image. The first 512KB of |
| 84 | * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading |
| 85 | * for OPTEE is paged image which only include the paging part using |
| 86 | * virtual memory but without "init" data. OPTEE will copy the "init" data |
| 87 | * (from pager image) to the first 512KB of TZC_DRAM, and then copy the |
| 88 | * extra image behind the "init" data. |
Konstantin Porotchkin | 5f8630b | 2020-06-19 17:48:48 +0200 | [diff] [blame] | 89 | */ |
Konstantin Porotchkin | 841ffeb | 2019-04-15 16:29:08 +0300 | [diff] [blame] | 90 | #define MARVELL_OPTEE_PAGEABLE_LOAD_BASE \ |
| 91 | (PLAT_MARVELL_TRUSTED_RAM_BASE + \ |
| 92 | PLAT_MARVELL_TRUSTED_RAM_SIZE - \ |
| 93 | MARVELL_OPTEE_PAGEABLE_LOAD_SIZE) |
| 94 | #define MARVELL_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 |
| 95 | #define MARVELL_OPTEE_PAGEABLE_LOAD_MEM \ |
| 96 | MAP_REGION_FLAT( \ |
| 97 | MARVELL_OPTEE_PAGEABLE_LOAD_BASE, \ |
| 98 | MARVELL_OPTEE_PAGEABLE_LOAD_SIZE, \ |
| 99 | MT_MEMORY | MT_RW | MT_SECURE) |
| 100 | |
| 101 | /* |
| 102 | * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging |
| 103 | * support is enabled). |
| 104 | */ |
| 105 | #define MARVELL_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ |
| 106 | BL32_BASE, \ |
| 107 | BL32_LIMIT - BL32_BASE, \ |
Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 108 | MT_MEMORY | MT_RW | MT_SECURE) |
Konstantin Porotchkin | 841ffeb | 2019-04-15 16:29:08 +0300 | [diff] [blame] | 109 | #endif /* SPD_opteed */ |
| 110 | |
Konstantin Porotchkin | 5f8630b | 2020-06-19 17:48:48 +0200 | [diff] [blame] | 111 | #define MARVELL_MAP_SECURE_RAM MAP_REGION_FLAT( \ |
| 112 | MARVELL_SHARED_RAM_BASE, \ |
| 113 | MARVELL_SHARED_RAM_SIZE, \ |
| 114 | MT_MEMORY | MT_RW | MT_SECURE) |
Konstantin Porotchkin | 841ffeb | 2019-04-15 16:29:08 +0300 | [diff] [blame] | 115 | |
Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 116 | #define MARVELL_MAP_DRAM MAP_REGION_FLAT( \ |
| 117 | MARVELL_DRAM_BASE, \ |
| 118 | MARVELL_DRAM_SIZE, \ |
| 119 | MT_MEMORY | MT_RW | MT_NS) |
| 120 | |
Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 121 | /* |
| 122 | * The number of regions like RO(code), coherent and data required by |
| 123 | * different BL stages which need to be mapped in the MMU. |
| 124 | */ |
| 125 | #if USE_COHERENT_MEM |
| 126 | #define MARVELL_BL_REGIONS 3 |
| 127 | #else |
| 128 | #define MARVELL_BL_REGIONS 2 |
| 129 | #endif |
| 130 | |
| 131 | #define MAX_MMAP_REGIONS (PLAT_MARVELL_MMAP_ENTRIES + \ |
| 132 | MARVELL_BL_REGIONS) |
| 133 | |
| 134 | #define MARVELL_CONSOLE_BAUDRATE 115200 |
| 135 | |
| 136 | /****************************************************************************** |
| 137 | * Required platform porting definitions common to all MARVELL std. platforms |
| 138 | *****************************************************************************/ |
| 139 | |
| 140 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 141 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
| 142 | |
| 143 | /* |
| 144 | * This macro defines the deepest retention state possible. A higher state |
| 145 | * id will represent an invalid or a power down state. |
| 146 | */ |
| 147 | #define PLAT_MAX_RET_STATE MARVELL_LOCAL_STATE_RET |
| 148 | |
| 149 | /* |
| 150 | * This macro defines the deepest power down states possible. Any state ID |
| 151 | * higher than this is invalid. |
| 152 | */ |
| 153 | #define PLAT_MAX_OFF_STATE MARVELL_LOCAL_STATE_OFF |
| 154 | |
| 155 | |
| 156 | #define PLATFORM_CORE_COUNT PLAT_MARVELL_CORE_COUNT |
| 157 | #define PLAT_NUM_PWR_DOMAINS (PLAT_MARVELL_CLUSTER_COUNT + \ |
| 158 | PLATFORM_CORE_COUNT) |
| 159 | |
| 160 | /* |
| 161 | * Some data must be aligned on the biggest cache line size in the platform. |
| 162 | * This is known only to the platform as it might have a combination of |
| 163 | * integrated and external caches. |
| 164 | */ |
| 165 | #define CACHE_WRITEBACK_GRANULE (1 << MARVELL_CACHE_WRITEBACK_SHIFT) |
| 166 | |
| 167 | |
| 168 | /******************************************************************************* |
| 169 | * BL1 specific defines. |
| 170 | * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of |
| 171 | * addresses. |
| 172 | ******************************************************************************/ |
| 173 | #define BL1_RO_BASE PLAT_MARVELL_TRUSTED_ROM_BASE |
| 174 | #define BL1_RO_LIMIT (PLAT_MARVELL_TRUSTED_ROM_BASE \ |
| 175 | + PLAT_MARVELL_TRUSTED_ROM_SIZE) |
| 176 | /* |
| 177 | * Put BL1 RW at the top of the Trusted SRAM. |
| 178 | */ |
| 179 | #define BL1_RW_BASE (MARVELL_BL_RAM_BASE + \ |
| 180 | MARVELL_BL_RAM_SIZE - \ |
| 181 | PLAT_MARVELL_MAX_BL1_RW_SIZE) |
| 182 | #define BL1_RW_LIMIT (MARVELL_BL_RAM_BASE + MARVELL_BL_RAM_SIZE) |
| 183 | |
| 184 | /******************************************************************************* |
| 185 | * BLE specific defines. |
| 186 | ******************************************************************************/ |
| 187 | #define BLE_BASE PLAT_MARVELL_SRAM_BASE |
| 188 | #define BLE_LIMIT PLAT_MARVELL_SRAM_END |
| 189 | |
| 190 | /******************************************************************************* |
| 191 | * BL2 specific defines. |
| 192 | ******************************************************************************/ |
| 193 | /* |
| 194 | * Put BL2 just below BL31. |
| 195 | */ |
| 196 | #define BL2_BASE (BL31_BASE - PLAT_MARVELL_MAX_BL2_SIZE) |
| 197 | #define BL2_LIMIT BL31_BASE |
| 198 | |
| 199 | /******************************************************************************* |
| 200 | * BL31 specific defines. |
| 201 | ******************************************************************************/ |
| 202 | /* |
| 203 | * Put BL31 at the top of the Trusted SRAM. |
| 204 | */ |
| 205 | #define BL31_BASE (MARVELL_BL_RAM_BASE + \ |
| 206 | MARVELL_BL_RAM_SIZE - \ |
| 207 | PLAT_MARVEL_MAX_BL31_SIZE) |
| 208 | #define BL31_PROGBITS_LIMIT BL1_RW_BASE |
| 209 | #define BL31_LIMIT (MARVELL_BL_RAM_BASE + \ |
| 210 | MARVELL_BL_RAM_SIZE) |
| 211 | |
Konstantin Porotchkin | 459366b | 2019-03-14 17:24:40 +0200 | [diff] [blame] | 212 | /******************************************************************************* |
| 213 | * BL32 specific defines. |
| 214 | ******************************************************************************/ |
Konstantin Porotchkin | 5f8630b | 2020-06-19 17:48:48 +0200 | [diff] [blame] | 215 | #define BL32_BASE PLAT_MARVELL_TRUSTED_RAM_BASE |
| 216 | #define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_RAM_SIZE) |
Konstantin Porotchkin | 459366b | 2019-03-14 17:24:40 +0200 | [diff] [blame] | 217 | |
| 218 | #ifdef SPD_none |
| 219 | #undef BL32_BASE |
| 220 | #endif /* SPD_none */ |
Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 221 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 222 | #endif /* MARVELL_DEF_H */ |