blob: 5813c8f8ce2198ae2ccc832389bf58dfa4070a88 [file] [log] [blame]
Tien Hock, Lohab34f742019-02-26 09:25:14 +08001/*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +08003 * Copyright (c) 2019, Intel Corporation. All rights reserved.
Tien Hock, Lohab34f742019-02-26 09:25:14 +08004 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
Tien Hock, Lohab34f742019-02-26 09:25:14 +08008#include <arch.h>
9#include <arch_helpers.h>
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +080010#include <assert.h>
Tien Hock, Lohab34f742019-02-26 09:25:14 +080011#include <common/bl_common.h>
Tien Hock, Lohab34f742019-02-26 09:25:14 +080012#include <drivers/arm/gicv2.h>
13#include <drivers/ti/uart/uart_16550.h>
Tien Hock, Lohab34f742019-02-26 09:25:14 +080014#include <lib/xlat_tables/xlat_tables.h>
15#include <lib/mmio.h>
16#include <plat/common/platform.h>
17#include <platform_def.h>
Tien Hock, Lohab34f742019-02-26 09:25:14 +080018
Hadi Asyrafi593c4c52019-12-17 19:22:17 +080019#include "socfpga_mailbox.h"
Hadi Asyrafif0fa8072019-10-23 17:02:55 +080020#include "socfpga_private.h"
Hadi Asyrafi67cb0ea2019-12-23 13:25:33 +080021#include "socfpga_reset_manager.h"
Hadi Asyrafi8ebd2372019-12-23 17:58:04 +080022#include "socfpga_system_manager.h"
Tien Hock, Lohab34f742019-02-26 09:25:14 +080023#include "s10_memory_controller.h"
24#include "s10_pinmux.h"
25#include "s10_clock_manager.h"
Tien Hock, Lohab34f742019-02-26 09:25:14 +080026
Hadi Asyrafi67cb0ea2019-12-23 13:25:33 +080027
Tien Hock, Lohab34f742019-02-26 09:25:14 +080028static entry_point_info_t bl32_image_ep_info;
29static entry_point_info_t bl33_image_ep_info;
30
31entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
32{
33 entry_point_info_t *next_image_info;
34
35 next_image_info = (type == NON_SECURE) ?
36 &bl33_image_ep_info : &bl32_image_ep_info;
37
38 /* None of the images on this platform can have 0x0 as the entrypoint */
39 if (next_image_info->pc)
40 return next_image_info;
41 else
42 return NULL;
43}
44
45void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
46 u_register_t arg2, u_register_t arg3)
47{
Andre Przywara98b5a112020-01-25 00:58:35 +000048 static console_t console;
Tien Hock, Lohab34f742019-02-26 09:25:14 +080049
50 console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
51 &console);
52 /*
53 * Check params passed from BL31 should not be NULL,
54 */
55 void *from_bl2 = (void *) arg0;
56
57 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
Tien Hock, Lohab34f742019-02-26 09:25:14 +080058 assert(params_from_bl2 != NULL);
Tien Hock, Lohab34f742019-02-26 09:25:14 +080059
60 /*
61 * Copy BL32 (if populated by BL31) and BL33 entry point information.
62 * They are stored in Secure RAM, in BL31's address space.
63 */
64
Hadi Asyrafic8a281c2019-10-24 16:13:09 +080065 if (params_from_bl2->h.type == PARAM_BL_PARAMS &&
66 params_from_bl2->h.version >= VERSION_2) {
67
68 bl_params_node_t *bl_params = params_from_bl2->head;
Tien Hock, Lohab34f742019-02-26 09:25:14 +080069
Hadi Asyrafic8a281c2019-10-24 16:13:09 +080070 while (bl_params) {
71 if (bl_params->image_id == BL33_IMAGE_ID)
72 bl33_image_ep_info = *bl_params->ep_info;
73
74 bl_params = bl_params->next_params_info;
75 }
76 } else {
77 struct socfpga_bl31_params *arg_from_bl2 =
78 (struct socfpga_bl31_params *) from_bl2;
79
80 assert(arg_from_bl2->h.type == PARAM_BL31);
81 assert(arg_from_bl2->h.version >= VERSION_1);
Tien Hock, Lohab34f742019-02-26 09:25:14 +080082
Hadi Asyrafic8a281c2019-10-24 16:13:09 +080083 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
84 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
Tien Hock, Lohab34f742019-02-26 09:25:14 +080085 }
86 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
87}
88
89static const interrupt_prop_t s10_interrupt_props[] = {
Hadi Asyrafi9f5dfc92019-10-23 16:26:53 +080090 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
91 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
Tien Hock, Lohab34f742019-02-26 09:25:14 +080092};
93
94static unsigned int target_mask_array[PLATFORM_CORE_COUNT];
95
96static const gicv2_driver_data_t plat_gicv2_gic_data = {
Hadi Asyrafi9f5dfc92019-10-23 16:26:53 +080097 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE,
98 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE,
Tien Hock, Lohab34f742019-02-26 09:25:14 +080099 .interrupt_props = s10_interrupt_props,
100 .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props),
101 .target_masks = target_mask_array,
102 .target_masks_num = ARRAY_SIZE(target_mask_array),
103};
104
105/*******************************************************************************
106 * Perform any BL3-1 platform setup code
107 ******************************************************************************/
108void bl31_platform_setup(void)
109{
110 /* Initialize the gic cpu and distributor interfaces */
111 gicv2_driver_init(&plat_gicv2_gic_data);
112 gicv2_distif_init();
113 gicv2_pcpu_distif_init();
114 gicv2_cpuif_enable();
Hadi Asyrafi0563a852019-10-22 12:59:32 +0800115
116 /* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */
117 mmio_write_64(PLAT_CPU_RELEASE_ADDR,
118 (uint64_t)plat_secondary_cpus_bl31_entry);
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800119
120 mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
Tien Hock, Lohab34f742019-02-26 09:25:14 +0800121}
122
123const mmap_region_t plat_stratix10_mmap[] = {
Hadi Asyrafiacee4882019-08-01 11:29:48 +0800124 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
125 MT_MEMORY | MT_RW | MT_NS),
126 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
127 MT_DEVICE | MT_RW | MT_NS),
128 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
129 MT_DEVICE | MT_RW | MT_SECURE),
Tien Hock, Lohab34f742019-02-26 09:25:14 +0800130 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
131 MT_NON_CACHEABLE | MT_RW | MT_SECURE),
132 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
133 MT_DEVICE | MT_RW | MT_SECURE),
Hadi Asyrafiacee4882019-08-01 11:29:48 +0800134 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
135 MT_DEVICE | MT_RW | MT_NS),
136 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
137 MT_DEVICE | MT_RW | MT_NS),
138 {0}
Tien Hock, Lohab34f742019-02-26 09:25:14 +0800139};
140
141/*******************************************************************************
142 * Perform the very early platform specific architectural setup here. At the
143 * moment this is only intializes the mmu in a quick and dirty way.
144 ******************************************************************************/
145void bl31_plat_arch_setup(void)
146{
147 const mmap_region_t bl_regions[] = {
148 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
149 MT_MEMORY | MT_RW | MT_SECURE),
150 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
151 MT_CODE | MT_SECURE),
152 MAP_REGION_FLAT(BL_RO_DATA_BASE,
153 BL_RO_DATA_END - BL_RO_DATA_BASE,
154 MT_RO_DATA | MT_SECURE),
155#if USE_COHERENT_MEM
156 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
157 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
158 MT_DEVICE | MT_RW | MT_SECURE),
159#endif
Hadi Asyrafiacee4882019-08-01 11:29:48 +0800160 {0}
Tien Hock, Lohab34f742019-02-26 09:25:14 +0800161 };
162
163 setup_page_tables(bl_regions, plat_stratix10_mmap);
164 enable_mmu_el3(0);
165}
166