Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 1 | /* |
Sieu Mun Tang | 8881ad0 | 2022-03-07 12:04:59 +0800 | [diff] [blame] | 2 | * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. |
Jit Loon Lim | 4c249f1 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 3 | * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #ifndef PLATFORM_DEF_H |
| 9 | #define PLATFORM_DEF_H |
| 10 | |
| 11 | #include <arch.h> |
| 12 | #include <common/interrupt_props.h> |
| 13 | #include <common/tbbr/tbbr_img_def.h> |
| 14 | #include <plat/common/common_def.h> |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 15 | #include "socfpga_plat_def.h" |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 16 | |
Sieu Mun Tang | 8881ad0 | 2022-03-07 12:04:59 +0800 | [diff] [blame] | 17 | /* Platform Type */ |
Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 18 | #define PLAT_SOCFPGA_STRATIX10 1 |
| 19 | #define PLAT_SOCFPGA_AGILEX 2 |
Sieu Mun Tang | 8881ad0 | 2022-03-07 12:04:59 +0800 | [diff] [blame] | 20 | #define PLAT_SOCFPGA_N5X 3 |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 21 | #define PLAT_SOCFPGA_AGILEX5 4 |
| 22 | #define SIMICS_RUN 1 |
| 23 | #define MAX_IO_MTD_DEVICES U(1) |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 24 | |
Hadi Asyrafi | 0563a85 | 2019-10-22 12:59:32 +0800 | [diff] [blame] | 25 | /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ |
| 26 | #define PLAT_CPU_RELEASE_ADDR 0xffd12210 |
| 27 | |
Hadi Asyrafi | 5fae68f | 2019-10-22 14:23:57 +0800 | [diff] [blame] | 28 | /* Magic word to indicate L2 reset is completed */ |
| 29 | #define L2_RESET_DONE_STATUS 0x1228E5E7 |
| 30 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 31 | /* Define next boot image name and offset */ |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 32 | /* Get non-secure image entrypoint for BL33. Zephyr and Linux */ |
| 33 | #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 |
| 34 | |
| 35 | #ifndef PRELOADED_BL33_BASE |
| 36 | #define PLAT_NS_IMAGE_OFFSET 0x80200000 |
| 37 | #else |
| 38 | #define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE |
| 39 | #endif |
| 40 | #define PLAT_HANDOFF_OFFSET 0x0003F000 |
| 41 | |
| 42 | #else |
Tien Hock, Loh | b1ab915 | 2019-10-14 14:48:24 +0800 | [diff] [blame] | 43 | #define PLAT_NS_IMAGE_OFFSET 0x10000000 |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 44 | #define PLAT_HANDOFF_OFFSET 0xFFE3F000 |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 45 | #endif |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 46 | |
| 47 | /******************************************************************************* |
| 48 | * Platform binary types for linking |
| 49 | ******************************************************************************/ |
| 50 | #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" |
| 51 | #define PLATFORM_LINKER_ARCH aarch64 |
| 52 | |
Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 53 | /* SoCFPGA supports up to 124GB RAM */ |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 54 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) |
| 55 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) |
| 56 | |
| 57 | |
| 58 | /******************************************************************************* |
| 59 | * Generic platform constants |
| 60 | ******************************************************************************/ |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 61 | #define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 |
| 62 | |
| 63 | /* Size of cacheable stacks */ |
| 64 | #define PLATFORM_STACK_SIZE 0x2000 |
| 65 | |
| 66 | /* PSCI related constant */ |
| 67 | #define PLAT_NUM_POWER_DOMAINS 5 |
| 68 | #define PLAT_MAX_PWR_LVL 1 |
| 69 | #define PLAT_MAX_RET_STATE 1 |
| 70 | #define PLAT_MAX_OFF_STATE 2 |
Deepika Bhavnani | dda01cb | 2019-12-13 10:50:36 -0600 | [diff] [blame] | 71 | #define PLATFORM_SYSTEM_COUNT U(1) |
| 72 | #define PLATFORM_CLUSTER_COUNT U(1) |
| 73 | #define PLATFORM_CLUSTER0_CORE_COUNT U(4) |
| 74 | #define PLATFORM_CLUSTER1_CORE_COUNT U(0) |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 75 | #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ |
| 76 | PLATFORM_CLUSTER0_CORE_COUNT) |
Deepika Bhavnani | dda01cb | 2019-12-13 10:50:36 -0600 | [diff] [blame] | 77 | #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 78 | |
| 79 | /* Interrupt related constant */ |
| 80 | |
Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 81 | #define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29 |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 82 | |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 83 | #define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8 |
| 84 | #define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9 |
| 85 | #define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10 |
| 86 | #define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11 |
| 87 | #define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12 |
| 88 | #define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13 |
| 89 | #define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14 |
| 90 | #define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15 |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 91 | |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 92 | #define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER |
| 93 | #define TSP_SEC_MEM_BASE BL32_BASE |
| 94 | #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 95 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 96 | |
| 97 | /******************************************************************************* |
| 98 | * BL31 specific defines. |
| 99 | ******************************************************************************/ |
| 100 | /* |
| 101 | * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if |
| 102 | * present). BL31_BASE is calculated using the current BL3-1 debug size plus a |
| 103 | * little space for growth. |
| 104 | */ |
| 105 | |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 106 | #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 107 | |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 108 | #define BL1_RO_BASE (0xffe00000) |
| 109 | #define BL1_RO_LIMIT (0xffe0f000) |
| 110 | #define BL1_RW_BASE (0xffe10000) |
| 111 | #define BL1_RW_LIMIT (0xffe1ffff) |
| 112 | #define BL1_RW_SIZE (0x14000) |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 113 | |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 114 | #define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET |
Hadi Asyrafi | a2edf0e | 2019-10-22 13:39:14 +0800 | [diff] [blame] | 115 | |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 116 | #define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16) |
| 117 | #define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8) |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 118 | |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 119 | #define CMP_ENTRY 0xFFE3EFF8 |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 120 | |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 121 | #define PLAT_SEC_WARM_ENTRY 0 |
Chee Hong Ang | 2382b11 | 2020-04-24 21:51:00 +0800 | [diff] [blame] | 122 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 123 | /******************************************************************************* |
| 124 | * Platform specific page table and MMU setup constants |
| 125 | ******************************************************************************/ |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 126 | #define MAX_XLAT_TABLES 8 |
| 127 | #define MAX_MMAP_REGIONS 16 |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 128 | |
| 129 | /******************************************************************************* |
| 130 | * Declarations and constants to access the mailboxes safely. Each mailbox is |
| 131 | * aligned on the biggest cache line size in the platform. This is known only |
| 132 | * to the platform as it might have a combination of integrated and external |
| 133 | * caches. Such alignment ensures that two maiboxes do not sit on the same cache |
| 134 | * line at any cache level. They could belong to different cpus/clusters & |
| 135 | * get written while being protected by different locks causing corruption of |
| 136 | * a valid mailbox address. |
| 137 | ******************************************************************************/ |
| 138 | #define CACHE_WRITEBACK_SHIFT 6 |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 139 | #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 140 | |
| 141 | /******************************************************************************* |
| 142 | * UART related constants |
| 143 | ******************************************************************************/ |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 144 | #define CRASH_CONSOLE_BASE PLAT_UART0_BASE |
| 145 | #define PLAT_INTEL_UART_BASE PLAT_UART0_BASE |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 146 | |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 147 | #define PLAT_BAUDRATE (115200) |
| 148 | #define PLAT_UART_CLOCK (100000000) |
Abdul Halim, Muhammad Hadi Asyrafi | f3a5d02 | 2020-06-29 12:15:27 +0800 | [diff] [blame] | 149 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 150 | /******************************************************************************* |
Tien Hock, Loh | 8d9e891 | 2019-10-02 13:49:25 +0800 | [diff] [blame] | 151 | * PHY related constants |
| 152 | ******************************************************************************/ |
| 153 | |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 154 | #define EMAC0_PHY_MODE PHY_INTERFACE_MODE_RGMII |
| 155 | #define EMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII |
| 156 | #define EMAC2_PHY_MODE PHY_INTERFACE_MODE_RGMII |
Tien Hock, Loh | 8d9e891 | 2019-10-02 13:49:25 +0800 | [diff] [blame] | 157 | |
| 158 | /******************************************************************************* |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 159 | * GIC related constants |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 160 | ******************************************************************************/ |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 161 | #define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE |
| 162 | #define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 163 | |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 164 | /******************************************************************************* |
| 165 | * System counter frequency related constants |
| 166 | ******************************************************************************/ |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 167 | |
| 168 | /* |
| 169 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 170 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 171 | * as Group 0 interrupts. |
| 172 | */ |
Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 173 | #define PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(grp) \ |
| 174 | INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER, \ |
| 175 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 176 | INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_0, \ |
| 177 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ |
| 178 | INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_1, \ |
| 179 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ |
| 180 | INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_2, \ |
| 181 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ |
| 182 | INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_3, \ |
| 183 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ |
| 184 | INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_4, \ |
| 185 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ |
| 186 | INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_5, \ |
| 187 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ |
| 188 | INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_6, \ |
| 189 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ |
| 190 | INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_7, \ |
| 191 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE) |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 192 | |
Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 193 | #define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp) |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 194 | |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 195 | #define MAX_IO_HANDLES 4 |
| 196 | #define MAX_IO_DEVICES 4 |
| 197 | #define MAX_IO_BLOCK_DEVICES 2 |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 198 | |
Hadi Asyrafi | c8a281c | 2019-10-24 16:13:09 +0800 | [diff] [blame] | 199 | #ifndef __ASSEMBLER__ |
| 200 | struct socfpga_bl31_params { |
| 201 | param_header_t h; |
| 202 | image_info_t *bl31_image_info; |
| 203 | entry_point_info_t *bl32_ep_info; |
| 204 | image_info_t *bl32_image_info; |
| 205 | entry_point_info_t *bl33_ep_info; |
| 206 | image_info_t *bl33_image_info; |
| 207 | }; |
| 208 | #endif |
| 209 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 210 | #endif /* PLATFORM_DEF_H */ |