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Bryan O'Donoghue4055aae2018-05-25 16:56:52 +01001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#ifndef __IMX_CSU_H__
7#define __IMX_CSU_H__
8
9#include <arch.h>
10
11/*
12 * Security Reference Manual for i.MX 7Dual and 7Solo Applications Processors,
13 * Rev. 0, 03/2017 Section 3.3.1
14 *
15 * Config secure level register (CSU_CSLn)
16 */
17#define CSU_CSL_LOCK_S1 BIT(24)
18#define CSU_CSL_NSW_S1 BIT(23)
19#define CSU_CSL_NUW_S1 BIT(22)
20#define CSU_CSL_SSW_S1 BIT(21)
21#define CSU_CSL_SUW_S1 BIT(20)
22#define CSU_CSL_NSR_S1 BIT(19)
23#define CSU_CSL_NUR_S1 BIT(18)
24#define CSU_CSL_SSR_S1 BIT(17)
25#define CSU_CSL_SUR_S1 BIT(16)
26#define CSU_CSL_LOCK_S2 BIT(8)
27#define CSU_CSL_NSW_S2 BIT(7)
28#define CSU_CSL_NUW_S2 BIT(6)
29#define CSU_CSL_SSW_S2 BIT(5)
30#define CSU_CSL_SUW_S2 BIT(4)
31#define CSU_CSL_NSR_S2 BIT(3)
32#define CSU_CSL_NUR_S2 BIT(2)
33#define CSU_CSL_SSR_S2 BIT(1)
34#define CSU_CSL_SUR_S2 BIT(0)
35
36#define CSU_CSL_OPEN_ACCESS (CSU_CSL_NSW_S1 | CSU_CSL_NUW_S1 | CSU_CSL_SSW_S1 |\
37 CSU_CSL_SUW_S1 | CSU_CSL_NSR_S1 | CSU_CSL_NUR_S1 |\
38 CSU_CSL_SSR_S1 | CSU_CSL_SUR_S1 | CSU_CSL_NSW_S2 |\
39 CSU_CSL_NUW_S2 | CSU_CSL_SSW_S2 | CSU_CSL_SUW_S2 |\
40 CSU_CSL_NSR_S2 | CSU_CSL_NUR_S2 | CSU_CSL_SSR_S2 |\
41 CSU_CSL_SUR_S2)
42void imx_csu_init(void);
43
44#endif /* __IMX_CSU_H__ */