| Lionel Debieve | 402a46b | 2019-11-04 12:28:15 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2019, STMicroelectronics - All Rights Reserved |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <errno.h> |
| 8 | |
| 9 | #include <drivers/nand.h> |
| 10 | #include <lib/utils.h> |
| 11 | #include <plat/common/platform.h> |
| 12 | |
| 13 | #define SZ_512 0x200U |
| 14 | |
| 15 | #if STM32MP_RAW_NAND |
| 16 | static int get_data_from_otp(struct nand_device *nand_dev) |
| 17 | { |
| 18 | int result; |
| 19 | uint32_t nand_param; |
| 20 | |
| 21 | /* Check if NAND parameters are stored in OTP */ |
| 22 | result = bsec_shadow_read_otp(&nand_param, NAND_OTP); |
| 23 | if (result != BSEC_OK) { |
| 24 | ERROR("BSEC: NAND_OTP Error %i\n", result); |
| 25 | return -EACCES; |
| 26 | } |
| 27 | |
| 28 | if (nand_param == 0U) { |
| 29 | return 0; |
| 30 | } |
| 31 | |
| 32 | if ((nand_param & NAND_PARAM_STORED_IN_OTP) == 0U) { |
| 33 | goto ecc; |
| 34 | } |
| 35 | |
| 36 | /* NAND parameter shall be read from OTP */ |
| 37 | if ((nand_param & NAND_WIDTH_MASK) != 0U) { |
| 38 | nand_dev->buswidth = NAND_BUS_WIDTH_16; |
| 39 | } else { |
| 40 | nand_dev->buswidth = NAND_BUS_WIDTH_8; |
| 41 | } |
| 42 | |
| 43 | switch ((nand_param & NAND_PAGE_SIZE_MASK) >> NAND_PAGE_SIZE_SHIFT) { |
| 44 | case NAND_PAGE_SIZE_2K: |
| 45 | nand_dev->page_size = 0x800U; |
| 46 | break; |
| 47 | |
| 48 | case NAND_PAGE_SIZE_4K: |
| 49 | nand_dev->page_size = 0x1000U; |
| 50 | break; |
| 51 | |
| 52 | case NAND_PAGE_SIZE_8K: |
| 53 | nand_dev->page_size = 0x2000U; |
| 54 | break; |
| 55 | |
| 56 | default: |
| 57 | ERROR("Cannot read NAND page size\n"); |
| 58 | return -EINVAL; |
| 59 | } |
| 60 | |
| 61 | switch ((nand_param & NAND_BLOCK_SIZE_MASK) >> NAND_BLOCK_SIZE_SHIFT) { |
| 62 | case NAND_BLOCK_SIZE_64_PAGES: |
| 63 | nand_dev->block_size = 64U * nand_dev->page_size; |
| 64 | break; |
| 65 | |
| 66 | case NAND_BLOCK_SIZE_128_PAGES: |
| 67 | nand_dev->block_size = 128U * nand_dev->page_size; |
| 68 | break; |
| 69 | |
| 70 | case NAND_BLOCK_SIZE_256_PAGES: |
| 71 | nand_dev->block_size = 256U * nand_dev->page_size; |
| 72 | break; |
| 73 | |
| 74 | default: |
| 75 | ERROR("Cannot read NAND block size\n"); |
| 76 | return -EINVAL; |
| 77 | } |
| 78 | |
| 79 | nand_dev->size = ((nand_param & NAND_BLOCK_NB_MASK) >> |
| 80 | NAND_BLOCK_NB_SHIFT) * |
| 81 | NAND_BLOCK_NB_UNIT * nand_dev->block_size; |
| 82 | |
| 83 | ecc: |
| 84 | switch ((nand_param & NAND_ECC_BIT_NB_MASK) >> |
| 85 | NAND_ECC_BIT_NB_SHIFT) { |
| 86 | case NAND_ECC_BIT_NB_1_BITS: |
| 87 | nand_dev->ecc.max_bit_corr = 1U; |
| 88 | break; |
| 89 | |
| 90 | case NAND_ECC_BIT_NB_4_BITS: |
| 91 | nand_dev->ecc.max_bit_corr = 4U; |
| 92 | break; |
| 93 | |
| 94 | case NAND_ECC_BIT_NB_8_BITS: |
| 95 | nand_dev->ecc.max_bit_corr = 8U; |
| 96 | break; |
| 97 | |
| 98 | case NAND_ECC_ON_DIE: |
| 99 | nand_dev->ecc.mode = NAND_ECC_ONDIE; |
| 100 | break; |
| 101 | |
| 102 | default: |
| 103 | if (nand_dev->ecc.max_bit_corr == 0U) { |
| 104 | ERROR("No valid eccbit number\n"); |
| 105 | return -EINVAL; |
| 106 | } |
| 107 | } |
| 108 | |
| 109 | VERBOSE("OTP: Block %i Page %i Size %lli\n", nand_dev->block_size, |
| 110 | nand_dev->page_size, nand_dev->size); |
| 111 | |
| 112 | return 0; |
| 113 | } |
| 114 | #endif |
| 115 | |
| 116 | #if STM32MP_RAW_NAND |
| 117 | int plat_get_raw_nand_data(struct rawnand_device *device) |
| 118 | { |
| 119 | device->nand_dev->ecc.mode = NAND_ECC_HW; |
| 120 | device->nand_dev->ecc.size = SZ_512; |
| 121 | |
| 122 | return get_data_from_otp(device->nand_dev); |
| 123 | } |
| 124 | #endif |
| 125 | |