blob: a3f08755acf8c5bbd87a48547b3ebd5e6e1c1d19 [file] [log] [blame]
Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Varun Wadekar0dc91812015-12-30 15:06:41 -08002 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05303 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __MEMCTRL_H__
32#define __MEMCTRL_H__
33
Varun Wadekarb316e242015-05-19 16:48:04 +053034void tegra_memctrl_setup(void);
Varun Wadekar6eec6d62016-03-03 13:28:10 -080035void tegra_memctrl_restore_settings(void);
Varun Wadekarb316e242015-05-19 16:48:04 +053036void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes);
Varun Wadekar0dc91812015-12-30 15:06:41 -080037void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes);
Varun Wadekar7a269e22015-06-10 14:04:32 +053038void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes);
Varun Wadekarb316e242015-05-19 16:48:04 +053039
40#endif /* __MEMCTRL_H__ */