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Konstantin Porotchkinede192d2018-10-08 16:48:52 +03001/*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00008#ifndef PHY_COMPHY_3700_H
9#define PHY_COMPHY_3700_H
Konstantin Porotchkinede192d2018-10-08 16:48:52 +030010
11#define PLL_SET_DELAY_US 600
12#define COMPHY_PLL_TIMEOUT 1000
13#define REG_16_BIT_MASK 0xFFFF
14
15#define COMPHY_SELECTOR_PHY_REG 0xFC
16/* bit0: 0: Lane0 is GBE0; 1: Lane1 is PCIE */
17#define COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT BIT(0)
18/* bit4: 0: Lane1 is GBE1; 1: Lane1 is USB3 */
19#define COMPHY_SELECTOR_USB3_GBE1_SEL_BIT BIT(4)
20/* bit8: 0: Lane1 is USB, Lane2 is SATA; 1: Lane2 is USB3 */
21#define COMPHY_SELECTOR_USB3_PHY_SEL_BIT BIT(8)
22
23/* SATA PHY register offset */
24#define SATAPHY_LANE2_REG_BASE_OFFSET 0x200
25
26/* USB3 PHY offset compared to SATA PHY */
27#define USB3PHY_LANE2_REG_BASE_OFFSET 0x200
28
29/* Comphy lane2 indirect access register offset */
30#define COMPHY_LANE2_INDIR_ADDR_OFFSET 0x0
31#define COMPHY_LANE2_INDIR_DATA_OFFSET 0x4
32
33/* PHY shift to get related register address */
34enum {
35 PCIE = 1,
36 USB3,
37};
38
39#define PCIEPHY_SHFT 2
40#define USB3PHY_SHFT 2
41#define PHY_SHFT(unit) ((unit == PCIE) ? PCIEPHY_SHFT : USB3PHY_SHFT)
42
43/* PHY register */
44#define COMPHY_POWER_PLL_CTRL 0x01
45#define PWR_PLL_CTRL_ADDR(unit) (COMPHY_POWER_PLL_CTRL * PHY_SHFT(unit))
46#define PU_IVREF_BIT BIT(15)
47#define PU_PLL_BIT BIT(14)
48#define PU_RX_BIT BIT(13)
49#define PU_TX_BIT BIT(12)
50#define PU_TX_INTP_BIT BIT(11)
51#define PU_DFE_BIT BIT(10)
52#define RESET_DTL_RX_BIT BIT(9)
53#define PLL_LOCK_BIT BIT(8)
54#define REF_FREF_SEL_OFFSET 0
55#define REF_FREF_SEL_MASK (0x1F << REF_FREF_SEL_OFFSET)
56#define REF_CLOCK_SPEED_25M (0x1 << REF_FREF_SEL_OFFSET)
57#define REF_CLOCK_SPEED_30M (0x2 << REF_FREF_SEL_OFFSET)
58#define PCIE_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_30M
59#define USB3_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_30M
60#define REF_CLOCK_SPEED_40M (0x3 << REF_FREF_SEL_OFFSET)
61#define REF_CLOCK_SPEED_50M (0x4 << REF_FREF_SEL_OFFSET)
62#define PHY_MODE_OFFSET 5
63#define PHY_MODE_MASK (7 << PHY_MODE_OFFSET)
64#define PHY_MODE_SATA (0x0 << PHY_MODE_OFFSET)
65#define PHY_MODE_PCIE (0x3 << PHY_MODE_OFFSET)
66#define PHY_MODE_SGMII (0x4 << PHY_MODE_OFFSET)
67#define PHY_MODE_USB3 (0x5 << PHY_MODE_OFFSET)
68
69#define COMPHY_KVCO_CAL_CTRL 0x02
70#define KVCO_CAL_CTRL_ADDR(unit) (COMPHY_KVCO_CAL_CTRL * PHY_SHFT(unit))
71#define USE_MAX_PLL_RATE_BIT BIT(12)
72#define SPEED_PLL_OFFSET 2
73#define SPEED_PLL_MASK (0x3F << SPEED_PLL_OFFSET)
74#define SPEED_PLL_VALUE_16 (0x10 << SPEED_PLL_OFFSET)
75
76#define COMPHY_RESERVED_REG 0x0E
77#define PHYCTRL_FRM_PIN_BIT BIT(13)
78
79#define COMPHY_LOOPBACK_REG0 0x23
80#define DIG_LB_EN_ADDR(unit) (COMPHY_LOOPBACK_REG0 * PHY_SHFT(unit))
81#define SEL_DATA_WIDTH_OFFSET 10
82#define SEL_DATA_WIDTH_MASK (0x3 << SEL_DATA_WIDTH_OFFSET)
83#define DATA_WIDTH_10BIT (0x0 << SEL_DATA_WIDTH_OFFSET)
84#define DATA_WIDTH_20BIT (0x1 << SEL_DATA_WIDTH_OFFSET)
85#define DATA_WIDTH_40BIT (0x2 << SEL_DATA_WIDTH_OFFSET)
86#define PLL_READY_TX_BIT BIT(4)
87
88#define COMPHY_SYNC_PATTERN_REG 0x24
89#define SYNC_PATTERN_REG_ADDR(unit) (COMPHY_SYNC_PATTERN_REG * \
90 PHY_SHFT(unit))
91#define TXD_INVERT_BIT BIT(10)
92#define RXD_INVERT_BIT BIT(11)
93
94#define COMPHY_SYNC_MASK_GEN_REG 0x25
95#define PHY_GEN_MAX_OFFSET 10
96#define PHY_GEN_MAX_MASK (3 << PHY_GEN_MAX_OFFSET)
97#define PHY_GEN_USB3_5G (1 << PHY_GEN_MAX_OFFSET)
98
99#define COMPHY_ISOLATION_CTRL_REG 0x26
100#define ISOLATION_CTRL_REG_ADDR(unit) (COMPHY_ISOLATION_CTRL_REG * \
101 PHY_SHFT(unit))
102#define PHY_ISOLATE_MODE BIT(15)
103
104#define COMPHY_MISC_REG0_ADDR 0x4F
105#define MISC_REG0_ADDR(unit) (COMPHY_MISC_REG0_ADDR * PHY_SHFT(unit))
106#define CLK100M_125M_EN BIT(4)
107#define CLK500M_EN BIT(7)
108#define PHY_REF_CLK_SEL BIT(10)
109#define MISC_REG0_DEFAULT_VALUE 0xA00D
110
111#define COMPHY_REG_GEN2_SET_2 0x3e
112#define GEN2_SETTING_2_ADDR(unit) (COMPHY_REG_GEN2_SET_2 * PHY_SHFT(unit))
113#define G2_TX_SSC_AMP_VALUE_20 BIT(14)
114#define G2_TX_SSC_AMP_OFF 9
115#define G2_TX_SSC_AMP_LEN 7
116#define G2_TX_SSC_AMP_MASK (((1 << G2_TX_SSC_AMP_LEN) - 1) << \
117 G2_TX_SSC_AMP_OFF)
118
119#define COMPHY_REG_GEN2_SET_3 0x3f
120#define GEN2_SETTING_3_ADDR(unit) (COMPHY_REG_GEN2_SET_3 * PHY_SHFT(unit))
121#define G3_TX_SSC_AMP_OFF 9
122#define G3_TX_SSC_AMP_LEN 7
123#define G3_TX_SSC_AMP_MASK (((1 << G2_TX_SSC_AMP_LEN) - 1) << \
124 G2_TX_SSC_AMP_OFF)
125#define G3_VREG_RXTX_MAS_ISET_OFF 7
126#define G3_VREG_RXTX_MAS_ISET_60U (0 << G3_VREG_RXTX_MAS_ISET_OFF)
127#define G3_VREG_RXTX_MAS_ISET_80U (1 << G3_VREG_RXTX_MAS_ISET_OFF)
128#define G3_VREG_RXTX_MAS_ISET_100U (2 << G3_VREG_RXTX_MAS_ISET_OFF)
129#define G3_VREG_RXTX_MAS_ISET_120U (3 << G3_VREG_RXTX_MAS_ISET_OFF)
130#define G3_VREG_RXTX_MAS_ISET_MASK (BIT(7) | BIT(8))
131#define RSVD_PH03FH_6_0_OFF 0
132#define RSVD_PH03FH_6_0_LEN 7
133#define RSVD_PH03FH_6_0_MASK (((1 << RSVD_PH03FH_6_0_LEN) - 1) << \
134 RSVD_PH03FH_6_0_OFF)
135
136#define COMPHY_REG_UNIT_CTRL_ADDR 0x48
137#define UNIT_CTRL_ADDR(unit) (COMPHY_REG_UNIT_CTRL_ADDR * \
138 PHY_SHFT(unit))
139#define IDLE_SYNC_EN BIT(12)
140#define UNIT_CTRL_DEFAULT_VALUE 0x60
141
142#define COMPHY_MISC_REG1_ADDR 0x73
143#define MISC_REG1_ADDR(unit) (COMPHY_MISC_REG1_ADDR * PHY_SHFT(unit))
144#define SEL_BITS_PCIE_FORCE BIT(15)
145
146#define COMPHY_REG_GEN3_SETTINGS_3 0x112
147#define COMPHY_GEN_FFE_CAP_SEL_MASK 0xF
148#define COMPHY_GEN_FFE_CAP_SEL_VALUE 0xF
149
150#define COMPHY_REG_LANE_CFG0_ADDR 0x180
151#define LANE_CFG0_ADDR(unit) (COMPHY_REG_LANE_CFG0_ADDR * \
152 PHY_SHFT(unit))
153#define PRD_TXDEEMPH0_MASK BIT(0)
154#define PRD_TXMARGIN_MASK (BIT(1) | BIT(2) | BIT(3))
155#define PRD_TXSWING_MASK BIT(4)
156#define CFG_TX_ALIGN_POS_MASK (BIT(5) | BIT(6) | BIT(7) | BIT(8))
157
158#define COMPHY_REG_LANE_CFG1_ADDR 0x181
159#define LANE_CFG1_ADDR(unit) (COMPHY_REG_LANE_CFG1_ADDR * \
160 PHY_SHFT(unit))
161#define PRD_TXDEEMPH1_MASK BIT(15)
162#define USE_MAX_PLL_RATE_EN BIT(9)
163#define TX_DET_RX_MODE BIT(6)
164#define GEN2_TX_DATA_DLY_MASK (BIT(3) | BIT(4))
165#define GEN2_TX_DATA_DLY_DEFT (2 << 3)
166#define TX_ELEC_IDLE_MODE_EN BIT(0)
167
168#define COMPHY_REG_LANE_STATUS1_ADDR 0x183
169#define LANE_STATUS1_ADDR(unit) (COMPHY_REG_LANE_STATUS1_ADDR * \
170 PHY_SHFT(unit))
171#define TXDCLK_PCLK_EN BIT(0)
172
173#define COMPHY_REG_LANE_CFG4_ADDR 0x188
174#define LANE_CFG4_ADDR(unit) (COMPHY_REG_LANE_CFG4_ADDR * \
175 PHY_SHFT(unit))
176#define SPREAD_SPECTRUM_CLK_EN BIT(7)
177
178#define COMPHY_REG_GLOB_PHY_CTRL0_ADDR 0x1C1
179#define GLOB_PHY_CTRL0_ADDR(unit) (COMPHY_REG_GLOB_PHY_CTRL0_ADDR * \
180 PHY_SHFT(unit))
181#define SOFT_RESET BIT(0)
182#define MODE_REFDIV 0x30
183#define MODE_CORE_CLK_FREQ_SEL BIT(9)
184#define MODE_PIPE_WIDTH_32 BIT(3)
185#define MODE_REFDIV_OFFSET 4
186#define MODE_REFDIV_LEN 2
187#define MODE_REFDIV_MASK (0x3 << MODE_REFDIV_OFFSET)
188#define MODE_REFDIV_BY_4 (0x2 << MODE_REFDIV_OFFSET)
189
190#define COMPHY_REG_TEST_MODE_CTRL_ADDR 0x1C2
191#define TEST_MODE_CTRL_ADDR(unit) (COMPHY_REG_TEST_MODE_CTRL_ADDR * \
192 PHY_SHFT(unit))
193#define MODE_MARGIN_OVERRIDE BIT(2)
194
195#define COMPHY_REG_GLOB_CLK_SRC_LO_ADDR 0x1C3
196#define GLOB_CLK_SRC_LO_ADDR(unit) (COMPHY_REG_GLOB_CLK_SRC_LO_ADDR * \
197 PHY_SHFT(unit))
198#define MODE_CLK_SRC BIT(0)
199#define BUNDLE_PERIOD_SEL BIT(1)
200#define BUNDLE_PERIOD_SCALE (BIT(2) | BIT(3))
201#define BUNDLE_SAMPLE_CTRL BIT(4)
202#define PLL_READY_DLY (BIT(5) | BIT(6) | BIT(7))
203#define CFG_SEL_20B BIT(15)
204
205#define COMPHY_REG_PWR_MGM_TIM1_ADDR 0x1D0
206#define PWR_MGM_TIM1_ADDR(unit) (COMPHY_REG_PWR_MGM_TIM1_ADDR * \
207 PHY_SHFT(unit))
208#define CFG_PM_OSCCLK_WAIT_OFF 12
209#define CFG_PM_OSCCLK_WAIT_LEN 4
210#define CFG_PM_OSCCLK_WAIT_MASK (((1 << CFG_PM_OSCCLK_WAIT_LEN) - 1) \
211 << CFG_PM_OSCCLK_WAIT_OFF)
212#define CFG_PM_RXDEN_WAIT_OFF 8
213#define CFG_PM_RXDEN_WAIT_LEN 4
214#define CFG_PM_RXDEN_WAIT_MASK (((1 << CFG_PM_RXDEN_WAIT_LEN) - 1) \
215 << CFG_PM_RXDEN_WAIT_OFF)
216#define CFG_PM_RXDEN_WAIT_1_UNIT (1 << CFG_PM_RXDEN_WAIT_OFF)
217#define CFG_PM_RXDLOZ_WAIT_OFF 0
218#define CFG_PM_RXDLOZ_WAIT_LEN 8
219#define CFG_PM_RXDLOZ_WAIT_MASK (((1 << CFG_PM_RXDLOZ_WAIT_LEN) - 1) \
220 << CFG_PM_RXDLOZ_WAIT_OFF)
221#define CFG_PM_RXDLOZ_WAIT_7_UNIT (7 << CFG_PM_RXDLOZ_WAIT_OFF)
222#define CFG_PM_RXDLOZ_WAIT_12_UNIT (0xC << CFG_PM_RXDLOZ_WAIT_OFF)
223
224/* SGMII */
225#define COMPHY_PHY_CFG1_OFFSET(lane) ((1 - (lane)) * 0x28)
226#define PIN_PU_IVEREF_BIT BIT(1)
227#define PIN_RESET_CORE_BIT BIT(11)
228#define PIN_RESET_COMPHY_BIT BIT(12)
229#define PIN_PU_PLL_BIT BIT(16)
230#define PIN_PU_RX_BIT BIT(17)
231#define PIN_PU_TX_BIT BIT(18)
232#define PIN_TX_IDLE_BIT BIT(19)
233#define GEN_RX_SEL_OFFSET 22
234#define GEN_RX_SEL_MASK (0xF << GEN_RX_SEL_OFFSET)
235#define GEN_TX_SEL_OFFSET 26
236#define GEN_TX_SEL_MASK (0xF << GEN_TX_SEL_OFFSET)
237#define PHY_RX_INIT_BIT BIT(30)
238#define SD_SPEED_1_25_G 0x6
239#define SD_SPEED_2_5_G 0x8
240
241/* COMPHY status reg:
242 * lane0: PCIe/GbE0 PHY Status 1
243 * lane1: USB3/GbE1 PHY Status 1
244 */
245#define COMPHY_PHY_STATUS_OFFSET(lane) (0x18 + (1 - (lane)) * 0x28)
246#define PHY_RX_INIT_DONE_BIT BIT(0)
247#define PHY_PLL_READY_RX_BIT BIT(2)
248#define PHY_PLL_READY_TX_BIT BIT(3)
249
250#define SGMIIPHY_ADDR(off, base) ((((off) & 0x00007FF) * 2) + (base))
251
252#define MAX_LANE_NR 3
253
254/* comphy API */
255int mvebu_3700_comphy_is_pll_locked(uint8_t comphy_index, uint32_t comphy_mode);
256int mvebu_3700_comphy_power_off(uint8_t comphy_index, uint32_t comphy_mode);
257int mvebu_3700_comphy_power_on(uint8_t comphy_index, uint32_t comphy_mode);
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000258#endif /* PHY_COMPHY_3700_H */