blob: ff0aaeb97c16a1ec4f52165d2d653af0c1d61faa [file] [log] [blame]
developer1033ea12019-04-10 21:09:26 +08001/*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch_helpers.h>
8#include <common/bl_common.h>
9#include <common/debug.h>
10#include <platform_def.h>
11#include <lib/utils.h>
12#include <lib/xlat_tables/xlat_tables.h>
13
14/* Table of regions to map using the MMU. */
15const mmap_region_t plat_mmap[] = {
16 /* for TF text, RO, RW */
17 MAP_REGION_FLAT(TZRAM_BASE, TZRAM_SIZE,
18 MT_MEMORY | MT_RW | MT_SECURE),
19 MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
20 MT_DEVICE | MT_RW | MT_SECURE),
21 MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE,
22 MT_DEVICE | MT_RW | MT_SECURE),
23 MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE,
24 MT_DEVICE | MT_RW | MT_SECURE),
25 { 0 }
26};
27
28/*******************************************************************************
29 * Macro generating the code for the function setting up the pagetables as per
30 * the platform memory map & initialize the mmu, for the given exception level
31 ******************************************************************************/
32void plat_configure_mmu_el3(uintptr_t total_base,
33 uintptr_t total_size,
34 uintptr_t ro_start,
35 uintptr_t ro_limit,
36 uintptr_t coh_start,
37 uintptr_t coh_limit)
38{
39 mmap_add_region(total_base, total_base, total_size,
40 MT_MEMORY | MT_RW | MT_SECURE);
41 mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
42 MT_MEMORY | MT_RO | MT_SECURE);
43 mmap_add_region(coh_start, coh_start, coh_limit - coh_start,
44 MT_DEVICE | MT_RW | MT_SECURE);
45 mmap_add(plat_mmap);
46 init_xlat_tables();
47 enable_mmu_el3(0);
48}
49
50unsigned int plat_get_syscnt_freq2(void)
51{
52 return SYS_COUNTER_FREQ_IN_TICKS;
53}