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Pankaj Gupta988bbb22020-12-09 14:02:40 +05301/*
Jiafei Panb27ac802021-07-20 17:14:32 +08002 * Copyright 2018-2021 NXP
Pankaj Gupta988bbb22020-12-09 14:02:40 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8#ifndef PLAT_COMMON_H
9#define PLAT_COMMON_H
10
11#include <stdbool.h>
12
Jiafei Panb27ac802021-07-20 17:14:32 +080013#include <dcfg.h>
Pankaj Gupta988bbb22020-12-09 14:02:40 +053014#include <lib/el3_runtime/cpu_data.h>
Jiafei Panb27ac802021-07-20 17:14:32 +080015
Pankaj Gupta988bbb22020-12-09 14:02:40 +053016#include <platform_def.h>
17
18#ifdef IMAGE_BL31
19
20#define BL31_END (uintptr_t)(&__BL31_END__)
21
22/*******************************************************************************
23 * This structure represents the superset of information that can be passed to
24 * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be
25 * populated only if BL2 detects its presence. A pointer to a structure of this
26 * type should be passed in X0 to BL31's cold boot entrypoint.
27 *
28 * Use of this structure and the X0 parameter is not mandatory: the BL31
29 * platform code can use other mechanisms to provide the necessary information
30 * about BL32 and BL33 to the common and SPD code.
31 *
32 * BL31 image information is mandatory if this structure is used. If either of
33 * the optional BL32 and BL33 image information is not provided, this is
34 * indicated by the respective image_info pointers being zero.
35 ******************************************************************************/
36typedef struct bl31_params {
37 param_header_t h;
38 image_info_t *bl31_image_info;
39 entry_point_info_t *bl32_ep_info;
40 image_info_t *bl32_image_info;
41 entry_point_info_t *bl33_ep_info;
42 image_info_t *bl33_image_info;
43} bl31_params_t;
44
45/* BL3 utility functions */
46void ls_bl31_early_platform_setup(void *from_bl2,
47 void *plat_params_from_bl2);
48/* LS Helper functions */
49unsigned int plat_my_core_mask(void);
50unsigned int plat_core_mask(u_register_t mpidr);
51unsigned int plat_core_pos(u_register_t mpidr);
52//unsigned int plat_my_core_pos(void);
53
54/* BL31 Data API(s) */
55void _init_global_data(void);
56void _initialize_psci(void);
57uint32_t _getCoreState(u_register_t core_mask);
58void _setCoreState(u_register_t core_mask, u_register_t core_state);
59
60/* SoC defined structure and API(s) */
61void soc_runtime_setup(void);
62void soc_init(void);
63void soc_platform_setup(void);
64void soc_early_platform_setup2(void);
65#endif /* IMAGE_BL31 */
66
67#ifdef IMAGE_BL2
68void soc_early_init(void);
69void soc_mem_access(void);
70void soc_preload_setup(void);
71void soc_bl2_prepare_exit(void);
72
73/* IO storage utility functions */
74int plat_io_setup(void);
75int open_backend(const uintptr_t spec);
76
77void ls_bl2_plat_arch_setup(void);
78void ls_bl2_el3_plat_arch_setup(void);
79
80enum boot_device {
81 BOOT_DEVICE_IFC_NOR,
82 BOOT_DEVICE_IFC_NAND,
83 BOOT_DEVICE_QSPI,
84 BOOT_DEVICE_EMMC,
85 BOOT_DEVICE_SDHC2_EMMC,
86 BOOT_DEVICE_FLEXSPI_NOR,
87 BOOT_DEVICE_FLEXSPI_NAND,
88 BOOT_DEVICE_NONE
89};
90
91enum boot_device get_boot_dev(void);
92
93/* DDR Related functions */
94#if DDR_INIT
95#ifdef NXP_WARM_BOOT
96long long init_ddr(uint32_t wrm_bt_flg);
97#else
98long long init_ddr(void);
99#endif
100#endif
101
102/* Board specific weak functions */
103bool board_enable_povdd(void);
104bool board_disable_povdd(void);
105
106void mmap_add_ddr_region_dynamically(void);
107#endif /* IMAGE_BL2 */
108
109typedef struct {
110 uint64_t addr;
111 uint64_t size;
112} region_info_t;
113
114typedef struct {
115 uint64_t num_dram_regions;
Jiafei Pan62661802021-10-21 15:17:51 +0800116 int64_t total_dram_size;
Pankaj Gupta988bbb22020-12-09 14:02:40 +0530117 region_info_t region[NUM_DRAM_REGIONS];
118} dram_regions_info_t;
119
120dram_regions_info_t *get_dram_regions_info(void);
121
122void ls_setup_page_tables(uintptr_t total_base,
123 size_t total_size,
124 uintptr_t code_start,
125 uintptr_t code_limit,
126 uintptr_t rodata_start,
127 uintptr_t rodata_limit
128#if USE_COHERENT_MEM
129 , uintptr_t coh_start,
130 uintptr_t coh_limit
131#endif
132);
133
Jiafei Panf0fe6832021-10-21 17:03:04 +0800134#define SOC_NAME_MAX_LEN (20)
135
Pankaj Gupta988bbb22020-12-09 14:02:40 +0530136/* Structure to define SoC personality */
137struct soc_type {
Jiafei Panf0fe6832021-10-21 17:03:04 +0800138 char name[SOC_NAME_MAX_LEN];
Jiafei Panb27ac802021-07-20 17:14:32 +0800139 uint32_t version;
140 uint8_t num_clusters;
141 uint8_t cores_per_cluster;
Pankaj Gupta988bbb22020-12-09 14:02:40 +0530142};
Jiafei Panb27ac802021-07-20 17:14:32 +0800143void get_cluster_info(const struct soc_type *soc_list, uint8_t ps_count,
144 uint8_t *num_clusters, uint8_t *cores_per_cluster);
Pankaj Gupta988bbb22020-12-09 14:02:40 +0530145
146#define SOC_ENTRY(n, v, ncl, nc) { \
147 .name = #n, \
Jiafei Panb27ac802021-07-20 17:14:32 +0800148 .version = SVR_##v, \
Pankaj Gupta988bbb22020-12-09 14:02:40 +0530149 .num_clusters = (ncl), \
150 .cores_per_cluster = (nc)}
151
152#endif /* PLAT_COMMON_H */