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Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +02001/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __HI3798cv200_H__
8#define __HI3798cv200_H__
9
Victor Chong539408d2018-01-03 01:53:08 +090010#include <utils_def.h>
11
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020012/* PL011 */
13#define PL011_UART0_BASE (0xF8B00000)
14#define PL011_BAUDRATE (115200)
15#define PL011_UART0_CLK_IN_HZ (75000000)
16
17/* Sys Counter */
18#define SYS_COUNTER_FREQ_IN_TICKS (24000000)
19#define SYS_COUNTER_FREQ_IN_MHZ (24)
20
21/* Timer */
22#define SEC_TIMER0_BASE (0xF8008000)
23#define TIMER00_LOAD (SEC_TIMER0_BASE + 0x000)
24#define TIMER00_VALUE (SEC_TIMER0_BASE + 0x004)
25#define TIMER00_CONTROL (SEC_TIMER0_BASE + 0x008)
26#define TIMER00_BGLOAD (SEC_TIMER0_BASE + 0x018)
27
28#define SEC_TIMER2_BASE (0xF8009000)
29#define TIMER20_LOAD (SEC_TIMER2_BASE + 0x000)
30#define TIMER20_VALUE (SEC_TIMER2_BASE + 0x004)
31#define TIMER20_CONTROL (SEC_TIMER2_BASE + 0x008)
32#define TIMER20_BGLOAD (SEC_TIMER2_BASE + 0x018)
33
34/* GPIO */
Victor Chong90f1ba32017-10-19 16:49:52 +090035#define GPIO_MAX (13)
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020036#define GPIO_BASE(x) (x != 5 ? \
37 0xf820000 + x * 0x1000 : 0xf8004000)
38
39/* SCTL */
40#define REG_BASE_SCTL (0xF8000000)
41#define REG_SC_GEN12 (0x00B0)
42
43/* CRG */
44#define REG_BASE_CRG (0xF8A22000)
45#define REG_CPU_LP (0x48)
46#define REG_CPU_RST (0x50)
47#define REG_PERI_CRG39 (0x9C)
48#define REG_PERI_CRG40 (0xA0)
49
50/* MCI */
51#define REG_BASE_MCI (0xF9830000)
52#define MCI_CDETECT (0x50)
53#define MCI_VERID (0x6C)
54#define MCI_VERID_VALUE (0x5342250A)
55#define MCI_VERID_VALUE2 (0x5342270A)
56
57/* EMMC */
58#define REG_EMMC_PERI_CRG REG_PERI_CRG40
59#define REG_SDCARD_PERI_CRG REG_PERI_CRG39
60#define EMMC_CLK_MASK (0x7 << 8)
61#define EMMC_SRST_REQ (0x1 << 4)
62#define EMMC_CKEN (0x1 << 1)
63#define EMMC_BUS_CKEN (0x1 << 0)
64#define EMMC_CLK_100M (0 << 8)
65#define EMMC_CLK_50M (1 << 8)
66#define EMMC_CLK_25M (2 << 8)
67
Victor Chong539408d2018-01-03 01:53:08 +090068#define EMMC_DESC_SIZE U(0x00100000) /* 1MB */
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020069#define EMMC_INIT_PARAMS(base) \
Haojian Zhuang3eff4092018-08-04 18:07:26 +080070 { .bus_width = MMC_BUS_WIDTH_8, \
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020071 .clk_rate = 25 * 1000 * 1000, \
Victor Chong539408d2018-01-03 01:53:08 +090072 .desc_base = (base), \
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020073 .desc_size = EMMC_DESC_SIZE, \
Haojian Zhuang3eff4092018-08-04 18:07:26 +080074 .flags = MMC_FLAG_CMD23, \
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020075 .reg_base = REG_BASE_MCI, \
76 }
77
78/* GIC-400 */
79#define GICD_BASE (0xF1001000)
80#define GICC_BASE (0xF1002000)
81#define GICR_BASE (0xF1000000)
82
83/* FIQ platform related define */
84#define HISI_IRQ_SEC_SGI_0 8
85#define HISI_IRQ_SEC_SGI_1 9
86#define HISI_IRQ_SEC_SGI_2 10
87#define HISI_IRQ_SEC_SGI_3 11
88#define HISI_IRQ_SEC_SGI_4 12
89#define HISI_IRQ_SEC_SGI_5 13
90#define HISI_IRQ_SEC_SGI_6 14
91#define HISI_IRQ_SEC_SGI_7 15
92#define HISI_IRQ_SEC_PPI_0 29
93#define HISI_IRQ_SEC_TIMER0 60
94#define HISI_IRQ_SEC_TIMER1 50
95#define HISI_IRQ_SEC_TIMER2 52
96#define HISI_IRQ_SEC_TIMER3 88
97#define HISI_IRQ_SEC_AXI 110
98
99/* Watchdog */
100#define HISI_WDG0_BASE (0xF8A2C000)
101
Jiancheng Xueb88b08a2017-08-28 18:55:43 +0800102#define HISI_TZPC_BASE (0xF8A80000)
103#define HISI_TZPC_SEC_ATTR_CTRL (HISI_TZPC_BASE + 0x10)
104
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +0200105#endif /* __HI3798cv200_H__ */