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Nariman Poushin0ece80f2018-02-26 06:52:04 +00001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8
9#include <platform_def.h>
10
11#include <common/bl_common.h>
12#include <common/debug.h>
13#include <drivers/arm/ccn.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000014#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <plat/common/platform.h>
Aditya Angadi20b48412019-04-16 11:29:14 +053016#include <drivers/arm/sbsa.h>
17#include <sgi_base_platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000018#include <services/secure_partition.h>
19
Nariman Poushin0ece80f2018-02-26 06:52:04 +000020#define SGI_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
21 V2M_FLASH0_SIZE, \
22 MT_DEVICE | MT_RO | MT_SECURE)
23/*
24 * Table of regions for different BL stages to map using the MMU.
25 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
26 * arm_configure_mmu_elx() will give the available subset of that.
27 *
28 * Replace or extend the below regions as required
29 */
30#if IMAGE_BL1
31const mmap_region_t plat_arm_mmap[] = {
32 ARM_MAP_SHARED_RAM,
33 SGI_MAP_FLASH0_RO,
34 CSS_SGI_MAP_DEVICE,
35 SOC_CSS_MAP_DEVICE,
36 {0}
37};
38#endif
39#if IMAGE_BL2
40const mmap_region_t plat_arm_mmap[] = {
41 ARM_MAP_SHARED_RAM,
42 SGI_MAP_FLASH0_RO,
43 CSS_SGI_MAP_DEVICE,
44 SOC_CSS_MAP_DEVICE,
45 ARM_MAP_NS_DRAM1,
46#if ARM_BL31_IN_DRAM
47 ARM_MAP_BL31_SEC_DRAM,
48#endif
Sughosh Ganue1579e02018-05-16 17:19:56 +053049#if ENABLE_SPM
50 ARM_SP_IMAGE_MMAP,
51#endif
Antonio Nino Diaz9b759862018-09-25 11:38:18 +010052#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
John Tsichritzis0c6ee742018-08-22 12:36:37 +010053 ARM_MAP_BL1_RW,
54#endif
Nariman Poushin0ece80f2018-02-26 06:52:04 +000055 {0}
56};
57#endif
58#if IMAGE_BL31
59const mmap_region_t plat_arm_mmap[] = {
60 ARM_MAP_SHARED_RAM,
61 V2M_MAP_IOFPGA,
62 CSS_SGI_MAP_DEVICE,
63 SOC_CSS_MAP_DEVICE,
Sughosh Ganue1579e02018-05-16 17:19:56 +053064#if ENABLE_SPM
65 ARM_SPM_BUF_EL3_MMAP,
66#endif
Nariman Poushin0ece80f2018-02-26 06:52:04 +000067 {0}
68};
Sughosh Ganue1579e02018-05-16 17:19:56 +053069
70#if ENABLE_SPM && defined(IMAGE_BL31)
71const mmap_region_t plat_arm_secure_partition_mmap[] = {
72 PLAT_ARM_SECURE_MAP_DEVICE,
73 ARM_SP_IMAGE_MMAP,
74 ARM_SP_IMAGE_NS_BUF_MMAP,
Sughosh Ganu70661cf2018-05-16 17:26:40 +053075 ARM_SP_CPER_BUF_MMAP,
Sughosh Ganue1579e02018-05-16 17:19:56 +053076 ARM_SP_IMAGE_RW_MMAP,
77 ARM_SPM_BUF_EL0_MMAP,
78 {0}
79};
80#endif /* ENABLE_SPM && defined(IMAGE_BL31) */
Nariman Poushin0ece80f2018-02-26 06:52:04 +000081#endif
82
83ARM_CASSERT_MMAP
Sughosh Ganue1579e02018-05-16 17:19:56 +053084
85#if ENABLE_SPM && defined(IMAGE_BL31)
86/*
87 * Boot information passed to a secure partition during initialisation. Linear
88 * indices in MP information will be filled at runtime.
89 */
90static secure_partition_mp_info_t sp_mp_info[] = {
91 [0] = {0x81000000, 0},
92 [1] = {0x81000100, 0},
93 [2] = {0x81000200, 0},
94 [3] = {0x81000300, 0},
95 [4] = {0x81010000, 0},
96 [5] = {0x81010100, 0},
97 [6] = {0x81010200, 0},
98 [7] = {0x81010300, 0},
99};
100
101const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = {
102 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
103 .h.version = VERSION_1,
104 .h.size = sizeof(secure_partition_boot_info_t),
105 .h.attr = 0,
106 .sp_mem_base = ARM_SP_IMAGE_BASE,
107 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
108 .sp_image_base = ARM_SP_IMAGE_BASE,
109 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
110 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
Ard Biesheuvel8b034fc2018-12-29 19:43:21 +0100111 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
Sughosh Ganue1579e02018-05-16 17:19:56 +0530112 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
113 .sp_image_size = ARM_SP_IMAGE_SIZE,
114 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
115 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
Ard Biesheuvel8b034fc2018-12-29 19:43:21 +0100116 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
Sughosh Ganue1579e02018-05-16 17:19:56 +0530117 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
118 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
119 .num_cpus = PLATFORM_CORE_COUNT,
120 .mp_info = &sp_mp_info[0],
121};
122
123const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
124{
125 return plat_arm_secure_partition_mmap;
126}
127
128const struct secure_partition_boot_info *plat_get_secure_partition_boot_info(
129 void *cookie)
130{
131 return &plat_arm_secure_partition_boot_info;
132}
133#endif /* ENABLE_SPM && defined(IMAGE_BL31) */
John Tsichritzis0c6ee742018-08-22 12:36:37 +0100134
Antonio Nino Diaz9b759862018-09-25 11:38:18 +0100135#if TRUSTED_BOARD_BOOT
John Tsichritzis0c6ee742018-08-22 12:36:37 +0100136int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
137{
138 assert(heap_addr != NULL);
139 assert(heap_size != NULL);
140
141 return arm_get_mbedtls_heap(heap_addr, heap_size);
142}
143#endif
Aditya Angadi20b48412019-04-16 11:29:14 +0530144
145void plat_arm_secure_wdt_start(void)
146{
147 sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
148}
149
150void plat_arm_secure_wdt_stop(void)
151{
152 sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
153}